I'm having difficulty with a design that uses an independent clock FIFO. I've attached the slow side of the clock to a global clock net running at a Lower frequency than the primary interface. I had previously used a programmable divider for the low speed interface, but I removed that to get cleaner synthesis. The IP works in the field.
What I'm seeing is that Vivado is reporting that a LUT is generating a lot of warnings:
A LUT 'debug_engine/u_debug/u_fifo_to_dut_i_1' is driving clock pin of 100 registers. This could lead to large hold time violations. First few involved registers are:
The part that makes no sense to me is that the clock pins in question are are supposed to be hooked up to a regional clock derived from a global clock:
When I open the implemented design, I see a lut (u_fifo_to_dut_i_1) that I didn't create. I also didn't create it implicitly.
My only theory is that some low-speed side IO's were brought over to the high side for debugging purposes. I connected those to the high side, just in case. The problem persists.
The FIFO in question is negative edge triggered. The data sheet for the FIFO says that I can do this by inverting the input clock and it will be 'absorbed' into the destination flops. My other theory is that the absorption isn't happening.