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haiqiu
Newbie
Newbie
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Registered: ‎09-08-2020

When add one gig_ethernet_pcs_pma IP in my block design, after change IP to LVDS serial Async/Sync mode, got "clock_selection" error

I use Vivado 2019.1, and when add one gig_ethernet_pcs_pma IP in my block design, after change IP to LVDS serial Async/Sync mode, got "clock_selection" error.

Detailed information as below:

set_property -dict [list CONFIG.Physical_Interface {LVDS} CONFIG.LvdsRefClk {625} CONFIG.ClockSelection {Async}] [get_bd_cells gig_ethernet_pcs_pma_0]
Sourcing the elaborate.xit file.
INFO: [xilinx.com:ip:gig_ethernet_pcs_pma:16.1-98989] design_ps_1_gig_ethernet_pcs_pma_0_0: ARCHITECTURE : zynquplus
INFO: [xilinx.com:ip:gig_ethernet_pcs_pma:16.1-98989] design_ps_1_gig_ethernet_pcs_pma_0_0: PART : xczu4cg-sfvc784-1-e
INFO: [xilinx.com:ip:gig_ethernet_pcs_pma:16.1-98989] design_ps_1_gig_ethernet_pcs_pma_0_0: SPEEDGRADE : -1
INFO: [xilinx.com:ip:gig_ethernet_pcs_pma:16.1-98989] design_ps_1_gig_ethernet_pcs_pma_0_0: Standard : SGMII
can't read "clock_selection": no such variable
ERROR: [IP_Flow 19-3554] GUI update of parameter PARAM_VALUE.ENABLEASYNCSGMII failed.can't read "clock_selection": no such variable

 

Could someone help to check the issue? Thanks.

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