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klchan
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Visitor
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Registered: ‎01-29-2021

Where can I find the offset address when using a Native BMG?

I want to use the Native Block Memory Generator without the AXI interface to access BRAM. Since this doesn't involve the AXI BRAM controller, nothing shows up in the Address Editor. Is there a way to configure the offset address, or find out what the offset address is?

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florentw
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Registered: ‎11-09-2015

Hi @klchan 

The address editor is to configure the addresses for the transaction going through AXI. If you do not have any AXI interface there is no point having the address.

In native you directly address the data in the BRAM. Not sure what offset you are looking for


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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klchan
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Registered: ‎01-29-2021

I want to use a C program to write to that location in BRAM (and then have the Block Memory Generator read from that location). However, I'd need to know what to set bram_pbase to (see code below), and it's different than the address(es) used as input to the BMG -- I was assuming there was some offset that was added, but I could be wrong. The C program is from Section 3.3 of this page: Accessing BRAM In Linux - Xilinx Wiki - Confluence (atlassian.net)

I've also attached the code below for easier reference:

#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <fcntl.h>
#include <sys/mman.h>
  
// Make the SDK console work in the debugger
#define printf(...) \
 fprintf(stdout, __VA_ARGS__); \
 fflush(stdout);
  
typedef long long int u64;
  
int main()
{
   unsigned int bram_size = 0x8000;
   off_t bram_pbase = 0xA0000000; // physical base address
   u64 *bram64_vptr;
   int fd;
  
   // Map the BRAM physical address into user space getting a virtual address for it
   if ((fd = open("/dev/mem", O_RDWR | O_SYNC)) != -1) {
  
      bram64_vptr = (u64 *)mmap(NULL, bram_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, bram_pbase);
  
      // Write to the memory that was mapped, use devmem from the command line of Linux to verify it worked
      // it could be read back here also
  
      bram64_vptr[0] = 0xDEADBEEFFACEB00C;
      close(fd);
   }
}

 

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florentw
Moderator
Moderator
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Registered: ‎11-09-2015

HI @klchan 

The processor use AXI to communicate to the PL. How are you planing to access the BRAM if no AXI interface?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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