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tv
Visitor
Visitor
448 Views
Registered: ‎06-16-2021

Why does a Xilinx IP not get flattened completely?

I see the answer to my question in: AR# 55989 - Vivado Synthesis - Why does a Xilinx IP not get flattened completely?

However, I need to be able to analyze and manipulate the implemented verilog netlist at the LUT level.

Even timing analysis stops at the CARRY8 instead of reporting delays through every LUT.

Is there any way to dump or generate the synthesized or implemented verilog netlist that only contains LUTs?

 

 

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drjohnsmith
Teacher
Teacher
428 Views
Registered: ‎07-09-2009

nope,

   The tools contain the intellectual data of Xilinx,

     of how the timings vary across the chips, and how different functons work

The way FPGA / tools work is that you specify the timing constraints, and your design, then the tools manipulate that informatoin to make a fgpa desing that meets your timing and fits in the FPGA.

One thign to note, 

    the tools stop when they have found a solution,

     the tools do NOT make the optimum / fastest / smallest design, they "just" meet your requirements

Why do you NEED to analyse the IP that is copyright of Xilinx at such a low level , are you trying to reverse engineer it ?

 

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tv
Visitor
Visitor
419 Views
Registered: ‎06-16-2021

No, just trying to optimize timing by manipulating LUT sizes, FO, pin ordering, function etc.

I'm able to accomplish a lot on manually generated RTL functions and was hoping to get it to work on simple 'A + B' verilog source too.

I guess I'll stick to custom coded functionality.

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avrumw
Expert
Expert
419 Views
Registered: ‎01-23-2009

Even timing analysis stops at the CARRY8 instead of reporting delays through every LUT.

It sounds like you are misunderstanding what the CARRY8 is. The CARRY8 is a cell - it is not implemented using LUTs. If you look at The UltraScale CLB User Guide (IG574) you can see a logical representation of the CARRY8 in figure 2-4 (but in reality the CARRY8 is probably not at all implemented this way - the logical representation shows this as a ripple carry, whereas the documentation clearly states that it is really a fast lookahead carry).

An UltraScale/UltraScale+ slice has

  • 8 6-input LUTs (that can be used in a variety of ways) PLUS
  • 16 flip-flops
  • 4xMUXF7, 2xMUXF8, 1xMUXF9
  • One CARRY8

All of these resources are separate and they are all indivisible - the CARRY8 is a single atomic cell.

Avrum

tv
Visitor
Visitor
289 Views
Registered: ‎06-16-2021

Thanks for the clarification Avrum.

Since I'm just doing some experimentation on manipulating LUTs, is there a way to disable the use of IP for synthesizing adders etc?

I realize that the resulting netlist will be very non-optimal, but I'm just trying to do some experimentation with controlling path delays through LUTs.

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drjohnsmith
Teacher
Teacher
276 Views
Registered: ‎07-09-2009

Are you by some chance doing a variant of the classic ring oscillator assignment,

Lots of post and info on this over the years

https://forums.xilinx.com/t5/Other-FPGA-Architecture/How-to-implement-a-ring-oscillator-with-routings-of-FPGA-Where/td-p/768444

 

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avrumw
Expert
Expert
261 Views
Registered: ‎01-23-2009

Since I'm just doing some experimentation on manipulating LUTs, is there a way to disable the use of IP for synthesizing adders etc?

First, to be clear the CARRY8 is not "IP", it is a cell just like the LUT is a cell. So this can't be answered generically. 

So I can try and answer the question "can you prevent the tool from using CARRY8". The answer is, "I'm not sure". The tools have the concept of a minimum threshold in terms of the width of the addition in order to use the CARRY8. It is trivially easy to show that using the CARRY8 for a 3 bit adder (or less) is useless; a 3 bit adder has 6 inputs, and hence fits in one LUT. Using the CARRY8 would require 3 LUTs plus the CARRY8 and would be slower. 

thought there was a way of changing this value at the time of synthesis. Some of the synthesis directives imply that they change this value, but there doesn't appear to be a direct mechanism to control it. However, it does appear to be able to change it on a block using BLOCK_SYNTHESIS - see UG901 "Using Block Synthesis Strategies". But this is somewhat of an advanced flow and has lots of other ramifications.

But as @drjohnsmith implied - you generally don't want to do any of this stuff. In conventional FPGA design, the use of the CARRY8 is highly beneficial and you would not want to turn it off.

Avrum