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Scholar
Scholar
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Registered: ‎06-20-2017

Why is phase alignment off by default for KUS, but not K7S

I noticed that by default in the clocking wizard on KUS (Kintex Ultrascale), the phase alignment is not checked by default, whereas it is on a K7S (Kintex 7S) project.

 

Also, the ZHOLD is auto on the KUS, but it is on the K7S.  I'm guessing ZHOLD might be automatically turned on to meet timing, but then again, I am not sure how that will work if OOC is enabled.

 

Note, this hasn't caused me any timing failures, just confusion when comparing a K7S design to a KUS design.

Mike
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Registered: ‎01-22-2015

Re: Why is phase alignment off by default for KUS, but not K7S

Hi Mike,

I noticed that by default in the clocking wizard on KUS (Kintex Ultrascale), the phase alignment is not checked by default, whereas it is on a K7S (Kintex 7S) project.
I'm not sure why Xilinx has changed the default setting for “phase alignment”.  However, I can guess – but first a little background.   In short, “phase alignment” for the MMCM or PLL means that extra resources are used to phase lock the output clock to the input clock (ref page 6 & 36, PG065).  These extra resources are typically extra clock tree resources and a clock buffer placed in the feedback path (CLKFBOUT to CLKFBIN) of the MMCM/PLL.  So, using “phase alignment” when you don’t need it wastes FPGA resources. 

Sometimes, we really need “phase alignment” (eg. in a source-synchronous interface when we use the MMCM/PLL to delay/advance the interface clock).  However, most often (I think) we are just “making clocks” with the MMCM/PLL - and we don’t really care that the clocks we make are phase aligned with the clock input to the MMCM/PLL – and therefore we don’t usually need “phase alignment”.   Maybe Xilinx took this into account when setting the default for “phase alignment” in UltraScale devices.  

Also, the ZHOLD is auto on the KUS, but it is on the K7S.  I'm guessing ZHOLD might be automatically turned on to meet timing, but then again, I am not sure how that will work if OOC is enabled.
ZHOLD is one of the COMPENSATION attributes for the MMCM/PLL (ref. Table 3-7 of UG472, Table 3-4 of UG572).  We are not allowed to select COMPENSATION for the MMCM/PLL in either 7-Series or UltraScale devices.  That is, the Vivado tools select the COMPENSATION setting for us based on what it ?thinks? we are doing. 

I agree with Avrum’s comments <here> that COMPENSATION=ZHOLD has some benefit for system synchronous interfaces.  However, the tools often select COMPENSATION=ZHOLD when we don’t want it and consequently ZHOLD often makes our job unnecessarily difficult.  That is, instead of the delays added by ZHOLD that supposedly help interfaces pass timing analysis, we usually wish we could turn ZHOLD off and construct any needed delays using other means (eg. IDELAY in data or clock path or another MMCM/PLL in clock path).

Cheers,
Mark

 

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