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Explorer
Explorer
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Registered: ‎08-21-2013

Why is the minimum FIFO depth 16?

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Is there any way to create a FIFO of depth less than 16?

I'm using a FIFO for clock domain crossing in an Artix 7 using Vivado Webpack 2018.3. The read and write ports are 32 bits wide. Since it is just for clock domain crossing, I only need a depth of say 4. I did not want to consume an 18 Kbit BRAM when I only need 128 bits, so I set it to "Independent Clocks Distributed RAM".

But the minimum depth is 16. That will consume alot more registers than necessary.

I looked at the MACRO XPM_FIFO_ASYNC and it says 16 is the minimum as well.

I'm porting from Altera Quartus where the minimum depth was 4. Not the end of the world if I can't do it, but seems like an arbitrary limitation.

 

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Adventurer
Adventurer
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Registered: ‎05-23-2018

That's because the short FIFOs are implemented in SRLs, not FDs. The SRLs are always either 16- or 32-Bit deep , independant of you wanting to use all of them or not.

This means that the FIFO for a given depth is optimized to give you the maximum amount of data for the used resources.

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Adventurer
Adventurer
1,181 Views
Registered: ‎05-23-2018

That's because the short FIFOs are implemented in SRLs, not FDs. The SRLs are always either 16- or 32-Bit deep , independant of you wanting to use all of them or not.

This means that the FIFO for a given depth is optimized to give you the maximum amount of data for the used resources.

View solution in original post

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Explorer
Explorer
1,161 Views
Registered: ‎08-21-2013
@klasha, it makes sense now. I went and read up on the SRL16 in UG474. It's not really wasting anything as I had worried. The Altera distributed FIFO's used FF.
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