03-03-2021 03:30 PM
Basically, my issue is that I'm writing 0xdeadbeefdeadbef0deadbef1deadbef2 to an address in BRAM (using the full AXI interface not lite). The write appears to work when I look at the simulation but then when I try to read the same address, what I get back is 0x000000000000000000000000deadbef2. I have no idea why the other bits either aren't written in the first place, or aren't being read back. What could be the cause of this? Any ideas? My bus data width is 128 bits and the address is 32. axlen is 0x00, axsize is 0b100. My first thought was that these were set incorrectly but I think its fine. Any suggestions would be helpful. I can provide more info if necessary but I'm sure the fix is something small I'm missing. Thank you!
Update: I tried modifying the address so that it would read from 000...01100 instead of 000...00000. (32 bit address) and it doesn't seem to make a difference. I'll keep trying things but any suggestions would be great!
03-10-2021 01:55 PM
03-10-2021 08:32 AM
03-10-2021 12:28 PM - edited 03-10-2021 02:36 PM
Here you go. A screenshot of the write and then the read. Ignore some of the extra signals. Note the BRAM signals at the bottom are for a different bram. The BRAM I'm having issues with is the one using the AXI interface. The Data I'm reading just isnt matching what was written. Let me know if there are other signals youd like to see.
I'll also add that I'm using a Nexys 4 DDR board and Vivado 2019.2.1.
03-10-2021 01:55 PM
03-10-2021 02:53 PM
I'm gonna accept this as the solution because reading that post helped me understand how the read and writes work. Basically I'm using this BRAM as memory for Microblaze but between microblaze and the BRAM is my own cache module I made. I did most of the signals correctly but i neglected WSTRB and was just passing in from microblaze. But microblaze only sent 32 bits so wstrb was 0x000F. I needed it to be 0xFFFF to tell that all 128 bits were valid. I just didn't understand all the signals properly. Thank you for pointing me in the right direction!
04-14-2021 09:54 PM
>but between microblaze and the BRAM is my own cache module I made.
Is this for testing or educational purposes? Because caching BRAM with BRAM can only make accesses to BRAM have more latency, unless the BRAM to be cached is clocked slower than the BRAM used in the cache. I guess you know that but in case you do not I thought I would mention it.
04-15-2021 11:11 AM
Yes its for educational purposes. The purpose of the BRAM is to replace DDR until I've finished. While running simulations with the DDR in my block diagram, theres no response because the DDR isn't actually there (at least this was my assumption).
So I plan to switch out the BRAM once I'm done.