cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
1,070 Views
Registered: ‎06-09-2018

'X' value in built in fifo simulation

Hi every body 

 

i want to simulation a built in fifo in vivado (this is very simple) but i get 'x' value  in full and empty output of fifo.

i use common clk built in fifo and this situation is appeared, but when i use common clk block ram every thing is ok.

what is the problem?

 

my files is attached.

Capture.PNG
0 Kudos
3 Replies
Highlighted
Explorer
Explorer
1,056 Views
Registered: ‎06-09-2018

i know that although in ug473, chapter 2 is said that WREN input should be held low for two clk period after RST deassertion but when i held it for 5 clk every thing ok. why is that so?

1.PNG
0 Kudos
Highlighted
Moderator
Moderator
1,034 Views
Registered: ‎08-08-2017

Hi @hrmt

 

Checked the Behavioral and Post Synthesis and Implementation Simulation at my end.

 

Behavioral Simulation:

1. Wr_en Assertion , 2 clock cycle after reset deassertion (Unexpected behavioral)

Capture2_clk.PNG

 

2. Wr_en Assertion , 5 (or more) clock cycle after reset deassertion (Expected Behavior)

 

cpatur5_clk.PNG

 

 

I will check this internally . Did you get a chance to perform the post Synthesis /Implementation Timing Simulation?

I have tried to run the post Synthesis Simulation bit getting error related to reset cycle.

 

post_syn.PNG

 

------------------------------------------------------------------------------------------------------------------------------------------------------

Reply if you have any Queries, Give Kudos and Accepts as solution if you get one

-------------------------------------------------------------------------------------------------------------------------------------------------------

 

 

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Explorer
Explorer
1,024 Views
Registered: ‎06-09-2018

Hi @pthakare

thanks for quick answer 

unfortunately when i see this behavior (this is unreliable), i use common clk block ram instead of built in fifo.

I will be very glad, if you know reason of it and tell to me.

0 Kudos