Is it possible to run the Xilinx XAUI IP core in a reduced speed mode? For 10GBaseT, which supports lower speed standards as well (1000BaseT, 100BaseT, etc), the IEEE standard states that the PHYs XAUI interface will switch down to a single lane at 1Gbps (i.e. SGMII for 1000BaseT), versus the normal mode of 3.125Gbps x 4 lanes for 10gig. Do you know if the Xilinx XAUI core can support this? I believe the Rocket IOs can be setup to support this, by using the DRP port to switch between the speeds (at least 10gig and 1gig) but I'm not sure about the XAUI.
The other 3 lanes are also running at 1gig, but the data is ignored.
Actually, a simpler way to do this is probably just to have a separate SGMII core specifically for the 1000BaseT mode. However, in that case, the lane 0 Rocket I/O needs to be able to operate in both the XAUI mode with a 156.25MHz reference clock, and in the SGMII mode with a 125MHz reference clock. I'd rather not have to switch reference clocks. It might be cleaner to just run with a 156.25MHz reference clock for both cases. Can I run the Rocket I/O using a 156.25MHz reference clock for Gigabit Ethernet? All the recommendations/examples say 125MHz but I wonder if this can be accomplished using a different divider or an 8 bit data path versus the normal 10 bit since 125MHz = 8/10 * 156.25MHz? Also, the spec says that a 10 bit path is required for 8B/10B encoded data, however, I think I can configure the PHY to shut this off, and since these are both parts on the same board, with the same reference clock, etc, that may be acceptable.