XPM_FIFO_AXIS Packet mode not working.

[timo-ge]

Hi,

I am trying to use XPM_FIFO_AXIS with packet mode enabled with Vivado 2018.1. The Fifo works, but Packet mode ist not working (see simulation waveform.)

I have instantiated the fifo as follows:

-- xpm_fifo_axis: AXI Stream FIFO
	-- Xilinx Parameterized Macro, version 2018.1
	xpm_fifo_axis_inst : xpm_fifo_axis
		generic map(
			CDC_SYNC_STAGES     => 2,   -- DECIMAL
			CLOCKING_MODE       => "common_clock", -- String
			ECC_MODE            => "no_ecc", -- String
			FIFO_DEPTH          => C_FIFO_DEPTH, -- DECIMAL
			FIFO_MEMORY_TYPE    => C_FIFO_MEMORY_TYPE, -- String
			PACKET_FIFO         => "true", -- String
			PROG_EMPTY_THRESH   => 5,   -- DECIMAL
			PROG_FULL_THRESH    => C_FIFO_PROG_FULL_THRESH, -- DECIMAL
			RD_DATA_COUNT_WIDTH => 1,   -- DECIMAL
			RELATED_CLOCKS      => 0,   -- DECIMAL
			TDATA_WIDTH         => 32,  -- DECIMAL
			TDEST_WIDTH         => 1,   -- DECIMAL
			TID_WIDTH           => 1,   -- DECIMAL
			TUSER_WIDTH         => 2,   -- DECIMAL
			USE_ADV_FEATURES    => "1002", -- String: enable prog_full flag
			WR_DATA_COUNT_WIDTH => 1    -- DECIMAL
		)
		port map(
			almost_empty_axis  => open,
			almost_full_axis   => open,
			dbiterr_axis       => open,
			prog_empty_axis    => open,
			prog_full_axis     => axis_prog_full,
			rd_data_count_axis => open,
			sbiterr_axis       => open,
			wr_data_count_axis => open,
			injectdbiterr_axis => '0',
			injectsbiterr_axis => '0',
			m_axis_tdest       => open,
			m_axis_tid         => open,
			m_axis_tkeep       => open,
			m_axis_tstrb       => open,
			-- master side
			m_aclk             => m_aclk,
			m_axis_tdata       => m_axis_tdata,
			m_axis_tlast       => m_axis_tlast,
			m_axis_tuser       => m_axis_tuser,
			m_axis_tready      => m_axis_tready,
			m_axis_tvalid      => m_axis_tvalid,
			-- slave side
			s_aclk             => m_aclk,
			s_aresetn          => s_aresetn,
			s_axis_tdest       => (others => '0'),
			s_axis_tid         => (others => '0'),
			s_axis_tkeep       => (others => '0'),
			s_axis_tstrb       => (others => '0'),
			s_axis_tdata       => s_axis_tdata,
			s_axis_tlast       => s_axis_tlast,
			s_axis_tuser       => s_axis_tuser,
			s_axis_tready      => s_axis_tready,
			s_axis_tvalid      => s_axis_tvalid
		);

[mokulanis]

I have problem with this too. Does anyone know solution?

[pthakare]

Hi @mokulanis & @timo-ge

As it is newly added Micro in the 2018.1 . I need to reproduce this issue at our end.  Please share the Complete Project file/ test bench written for share RTL instantiation.

[timo-ge]

I found, that the error is in

/opt/Xilinx/Vivado/2018.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv

Line 2306 and following:

generate if (P_PKT_MODE == 1 && P_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc
    assign axis_wr_eop = s_axis_tvalid & s_axis_tready & s_axis_tlast;
    assign axis_rd_eop = m_axis_tvalid & m_axis_tready & m_axis_tlast & axis_pkt_read;

    always @ (posedge s_aclk) begin
      if (rst_axis)
        axis_pkt_read    <= 1'b0;
      else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)
        axis_pkt_read    <= 1'b0;
      else if ((axis_pkt_cnt > 0) || (almost_full_axis && m_axis_tvalid))
        axis_pkt_read    <= 1'b1;
    end

    always @ (posedge s_aclk) begin
      if (rst_axis)
        axis_wr_eop_d1    <= 1'b0;
      else
        axis_wr_eop_d1   <= axis_wr_eop;
    end

    always @ (posedge s_aclk) begin
      if (rst_axis)
        axis_pkt_cnt    <= 0;
      else if (axis_wr_eop_d1 && ~axis_rd_eop)
        axis_pkt_cnt    <= axis_pkt_cnt + 1;
      else if (axis_rd_eop && ~axis_wr_eop_d1)
        axis_pkt_cnt    <= axis_pkt_cnt - 1;
    end
  end endgenerate // gaxis_pkt_fifo_cc

There is the code for the packet mode, which drives the signal axis_pkt_read.

But this signal is never read. Definitively a really annoying bug from Xilinx!

[pthakare]

Hi @timo-ge and @mokulanis

I had a discussion with factory engineers on enabling the packet mode in XPM_FIFO _AXIS.

Async clocking mode Is not supported when packet mode is enabled in AXI4-stream data fifo and XPM_FIFO_AXIS.

Currently the IP core utilizes FIFO Generator  core for the FIFO operation, In 2018.3, Development team is planning  migrate AXI4-Stream Data FIFO to use xpm_fifo_axis instead of FIFO Generator in order to support future devices. 

xpm_fifo_axis will support async packet mode in 2018.3.

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Reply if you have any queries, Give Kudos and Accepts as Solution

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[pthakare]

Hi @timo-ge @mokulanis

Packet mode will support in 2018.3

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Give Kudos and accepts as Solution

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