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k81601
Observer
Observer
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Registered: ‎07-02-2018

XPM FIFO AXIS in packet mode not working properly

Hello,

I am using xpm_fifo_axi to cross clock domains with AXIS. I need output to be valid (TVALID asserted) for the whole packet - from the first assertion of TVALID to TLAST.

It is doing great except one particular situation when packet consists of two valid words. Once upon a time TVALID drops in between those two words as you can see on the screenshot (one for correct behavior and one for incorrect behavior). I think this is caused by the mechanism which determine if there is packet in the fifo as it cross clock domain as well (it could outrun second axis word before it cross clock domain).

Output stream is correctOutput stream is correct

Output stream is invalid in the middle of the packetOutput stream is invalid in the middle of the packet

My question is - is this expected behavior (or known problem).

Thank you.

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florentw
Moderator
Moderator
409 Views
Registered: ‎11-09-2015

Hi @k81601 

I do not think this is a bad behaviour. There is nothing that says that tvalid cannot go low during a packet transmission.

What would be interesting to see might be the input. This delay might be coming from there as well


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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