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chsdkj
Explorer
Explorer
2,033 Views
Registered: ‎07-10-2013

XPM_FIFO Macros' Resetting

1) UG974 (v2017.4) provides some description of the reset behavior of the XPM_FIFO_SYNC macro, mostly in Fig2-9 on p.48.  Please confirm the following, which appears to be the case, but is apparently not well spelled-out in the document:

 

a) The WR_RST_BUSY and RD_RST_BUSY outputs are identical to each other, and are a 1-CLK-cycle-delayed version of the RST input, including no matter low long RST is held asserted.

 

b) The WR_EN input needs to kept deasserted (electrically low) during the reset sequence starting in the cycle in which the RST input is asserted, through to and including the cycle in which the WR_RST_BUSY and RD_RST_BUSY outputs are first false following having been true.

 

c) The RD_EN input needs to kept deasserted (electrically low) during the reset sequence starting in the cycle in which the RST input is asserted, through to and including the cycle in which the WR_RST_BUSY and RD_RST_BUSY outputs are first false following having been true, and for two additional cycles as well.

 

2) Similarly, some description is provided of the reset behavior of the XPM_FIFO_ASYC macro, mostly in Fig2-1 on p.34.  Please confirm the following, which appears to be the case, but is apparently not well spelled-out in the document:

 

d) The WR_RST_BUSY output is a 1-WR_CLK-cycle-delayed version of the RST input, including no matter low long RST is held asserted.

 

e) The WR_EN input needs to kept deasserted (electrically low) during the reset sequence starting in the WR_CLK cycle in which the RST input is asserted, through to and including the WR_CLK cycle in which the WR_RST_BUSY output is first false following having been true.

 

f) The RD_RST_BUSY output is asserted a number of RD_CLK cycles (related to the CDC_SYNC_STAGES attribute value) after the WR_RESET_BUSY input was observed to first become asserted.

 

g) The RD_RST_BUSY output, once asserted, stays asserted for a total of exactly two (2) RD_CLK cycles.

 

g') Or, is it that the RD_RST_BUSY output, once asserted, stays asserted for a number of RD_CLK cycles that is related to the value of the CDC_SYNC_STAGES attribute (which has a default value of 2)?

 

h) The RD_EN input needs to kept deasserted (electrically low) during the reset sequence starting in the RD_CLK cycle in which the RD_RESET_BUSY output is true, through to and including the RD_CLK cycle in which the RD_RST_BUSY output is first false following having been true, and for two additional RD_CLK cycles as well.

 

3) Why does the UG974 description of the primitive(s) upon which the XPM_FIFO macros are (presumably) based (p.208-222) have no similar discussion or details diagrams of timings similar to those presented for the XPM_FIFO macros?  Are the XPM_FIFO macros' reset timings/issues not applicable to those primitives?

 

4) And, same as 3) above but for the UG573 (v1.8) description of the primitives' behavior (p.50-89): Are the XPM_FIFO macros' reset timings/issues not applicable?

 

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vemulad
Xilinx Employee
Xilinx Employee
1,975 Views
Registered: ‎09-20-2012

Hi @chsdkj

 

If rst is asserted, the wr_rst_busy output asserts immediately after the rising edge of wr_clk, and remains asserted until the reset operation is complete. Following the assertion of wr_rst_busy, the internal reset is synchronized to the rd_clk domain. Upon arrival in the rd_clk domain, the rd_rst_busy is asserted and is held asserted until the resetting of all rd_clk domain signals is complete. At this time, rd_rst_busy is deasserted.

 

wr_en/rd_en must be low when rst or wr_rst_busy or rd_rst_busy is high.

 

Refer to Figure 2-1 in https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug974-vivado-ultrascale-libraries.pdf

Thanks,
Deepika.
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pice
Observer
Observer
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Registered: ‎07-18-2017

Dear @vemulad 

I'm a bit confused: to allow the rd_en to be low during rd_rst_busy and wr_rst_busy is high, the wr_rst_busy signal must be synchronized between the two clock domains. I thought the feature of XMP_ASYNC_FIFO is to provide a interface between two clock domains. If wr_en/rd_en must be low when rst or wr_rst_busy or rd_rst_busy is high one need additional logic for CDC.

It would be easier if rd_en just depends on rd_rst_busy signal. (assuming RST was asserted once)

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