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Observer
Observer
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Registered: ‎03-20-2018

XPM_MEMORY_TDPRAM Use UltraRAM Embedded Output Registers

Hello,

I use Vivado 2018.1. I'm currently instantiating UltraRAM using the macro, XPM_MEMORY_TDPRAM.  My memory has a cascade height of 4 and READ_LATENCY_A/B is 2.

I would like to use the UltraRAM's embedded output register, but according to the library guide, the UltraRAM's embedded registers aren't used unless READ_LATENCY_A/B >= cascade height.

Is there a way around this rule? I don't want my memory instantiation to use an FDRE; instead I would like it to use the embedded OREG_A/B.

 

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Community Manager
Community Manager
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Registered: ‎08-08-2007

Re: XPM_MEMORY_TDPRAM Use UltraRAM Embedded Output Registers

Hi @ty.wadd 

I found this Design and Debug blog an interesting read around Latency/Pipelining, you may also find it useful. 

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Achieving-optimal-timing-performance-by-automatic-pipelining-of/ba-p/971760

The optimal pipelining depends on your max frequency. With a Read_Latency of 2 you need the OREG and FD.

 

Sandy 

Thanks,
Sandy

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Observer
Observer
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Registered: ‎03-20-2018

Re: XPM_MEMORY_TDPRAM Use UltraRAM Embedded Output Registers

Thanks for your reply, Sandy.

I've given it a read and it is helpful.  In my case, only an OREG is necessary.  However, the XPM_MEMORY_TDPRAM is not instantiating my UltraRAM with an OREG.  It instead opts to use only an FD; this is the issue. How can I get XPM_MEMORY to use the OREG instead of the FD?

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