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awoz92gmu
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Registered: ‎11-26-2018

XPM library: Failing synthesis because of xpm_memory.sv

I'm trying to synthesize my design with the XPM library, my synthesis tool is Synplify Pro. 

I'm only using the XPM synchonous fifo in my design (xpm_fifo_sync.sv), they're systemVerilog files. 

These files can be found in the Vivado install directory  C:\Programs\Xilinx\Vivado\2018.2\data\ip\xpm\

 

My build is failing on some code in xpm_memory.sv

I've attached an image of the error message and of the code from xpm_memory.sv that's causing the failure. 

 

I haven't altered this file so I don't understand why it would be causing this failure, any ideas?

 

Thanks in advance. 

xpm_failure.PNG
xpm_memory_snippit.PNG
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pthakare
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Registered: ‎08-08-2017

Hi @awoz92gmu 

Please share you XPM_FIFO_SYNC  instatiation to check this at our end .  It seems the value of one of the parameter is not set correctly and this cause synthesis error corresponding to out of range value for rst_val_conv_a_i/

 

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awoz92gmu
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Registered: ‎11-26-2018

 

component xpm_fifo_sync
generic (

-- Common module generics
FIFO_MEMORY_TYPE : string := "block";
FIFO_WRITE_DEPTH : integer := 2048;
WRITE_DATA_WIDTH : integer := 32;
READ_MODE : string :="std";
FIFO_READ_LATENCY : integer := 1;
FULL_RESET_VALUE : integer := 0;
READ_DATA_WIDTH : integer := 32;
WR_DATA_COUNT_WIDTH : integer := 12;
PROG_FULL_THRESH : integer := 10;
RD_DATA_COUNT_WIDTH : integer := 12;
PROG_EMPTY_THRESH : integer := 10;
DOUT_RESET_VALUE : string := "0";
ECC_MODE : string :="no_ecc";
WAKEUP_TIME : integer := 0
);
port (

sleep : in std_logic;
rst : in std_logic;
wr_clk : in std_logic;
wr_en : in std_logic;
din : in std_logic_vector(WRITE_DATA_WIDTH-1 downto 0);
full : out std_logic;
prog_full : out std_logic;
wr_data_count : out std_logic_vector(WR_DATA_COUNT_WIDTH-1 downto 0);
overflow : out std_logic;
wr_rst_busy : out std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(READ_DATA_WIDTH-1 downto 0);
empty : out std_logic;
prog_empty : out std_logic;
rd_data_count : out std_logic_vector(RD_DATA_COUNT_WIDTH-1 downto 0);
underflow : out std_logic;
rd_rst_busy : out std_logic;
injectsbiterr : in std_logic;
injectdbiterr : in std_logic;
sbiterr : out std_logic;
dbiterr : out std_logic
);


begin

 

xpm_fifo_sync_inst : xpm_fifo_sync
generic map (
DOUT_RESET_VALUE => "0", -- String
ECC_MODE => "no_ecc", -- String
FIFO_MEMORY_TYPE => "block", -- String
FIFO_READ_LATENCY => 1, -- DECIMAL
FIFO_WRITE_DEPTH => 2**AddrSize, -- DECIMAL
FULL_RESET_VALUE => 0, -- DECIMAL
PROG_EMPTY_THRESH => AEmptyLoc, -- DECIMAL
PROG_FULL_THRESH => 2**AddrSize - AFullLoc - 1, -- DECIMAL
RD_DATA_COUNT_WIDTH => AddrSize, -- DECIMAL
READ_DATA_WIDTH => BusWidth, -- DECIMAL
READ_MODE => "std", -- String
USE_ADV_FEATURES => "0707", -- String
WAKEUP_TIME => 0, -- DECIMAL
WRITE_DATA_WIDTH => BusWidth, -- DECIMAL
WR_DATA_COUNT_WIDTH => AddrSize -- DECIMAL
)
port map (
almost_empty => FifoAEmpty, 
almost_full => FifoAFull,
data_valid => readValid, 
dbiterr => open, 
dout => ReadData, 
empty => FifoEmpty, 
full => FifoFull,
overflow => open,
prog_empty => open,
prog_full => open, 
rd_data_count => open,
rd_rst_busy => rd_rst_busy, 
sbiterr => open, 
underflow => open, 
wr_ack => open, 
wr_data_count => Count,
wr_rst_busy => wr_rst_busy, 
din => WriteData,
injectdbiterr => '0',
injectsbiterr => '0',
rd_en => RE,
rst => reset,
sleep => '0',
wr_clk => Clk, 
wr_en => WE 
);

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awoz92gmu
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Registered: ‎11-26-2018

@pthakare thanks for the reply. When you say parameters do you mean one of the attributes was set incorrectly? 

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awoz92gmu
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Registered: ‎11-26-2018

Also I don't understand how to set the "USE_ADV_FEATURES" attribute, the default is "0707" but I'm not sure I understand the description in ug974. 

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awoz92gmu
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Registered: ‎11-26-2018

@pthakare any ideas of things I should try? I've gone through all my generics and I/O and I can't figure out what I'm setting incorrectly to cause this error. 

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pthakare
Moderator
Moderator
861 Views
Registered: ‎08-08-2017

Hi @awoz92gmu 

I have tried to reproduce your issue but stuck  because you have not shared the the parameter values ,buswidth , addrsize etc,  is it posssible for you to share a small test case (VIVADO project ) to check in here and discuss internally .  Additionally is synthesis using VIVADO synthesis tool giving the same error ?

I sent you the FTP link to share the test case.

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awoz92gmu
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Registered: ‎11-26-2018

@pthakare thanks for looking into this. 

That's actually part of the problem, the FIFO component in which I use xpm_fifo_sync is used at least 100 times in my design and the generics BusWidth and AddrSize are often different for each instantiation. So I don't know exactly where the problem is being caused.  Thier defaults are (BusWidth : positive := 9; AddrSize : positive := 11;). My build environment is not currently setup to synthesize with Vivado, only Snynplify. I have a feeling this "index out of range" error wouldn't show up if sythesizing with Vivado, especially since it's a Synplify error (CS101) but that's just a guess.  

I will take a look at the test case you sent. 

I can't share much because of company policy, but I could try creating a small Vivado project as a test case. 

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