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dimpy
Adventurer
Adventurer
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Registered: ‎06-05-2020

ZC-706 block design and constraints

Hello,

I working on ZC-706. I have took one DVB-s2 code from GitHub (which is attached)  and trying to export RTL. I have created project in vivado_hls  and export the RTL successfully. Using vivado hlx I have import the created ip into this and tried to create block design for zc-706.

Kindly help me which ip blocks are necessary for ZC-706?

Also find the below warnings.

WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial
circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate dvbs2rate:solution1 22-Sep-2020, 3:58:34 PM
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in
flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis
constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. dvbs2rate:solution1 22-Sep-2020, 3:56:18 PM
Warning: Parallel synthesis criteria is not met
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 854.184
; gain = 482.105
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 923.863 ; gain
= 551.785
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 923.863 ; gain = 551.785
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 933.398 ; gain = 561.320
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 933.398 ; gain = 561.320
---------------------------------------------------------------------------------

Report Check Netlist:
+------+------------------+-------+---------+-------+------------------+
| |Item |Errors |Warnings |Status |Description |
+------+------------------+-------+---------+-------+------------------+
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 933.398 ; gain
= 561.320
---------------------------------------------------------------------------------

Report RTL Partitions:
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 933.398 ; gain = 561.320
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 933.398 ; gain = 561.320
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 933.398 ; gain =
561.320
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 933.398 ; gain = 561.320
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes:
+------+----------------+----------+
| |BlackBox name |Instances |
+------+----------------+----------+
|1 |bd_0_hls_inst_0 | 1|
+------+----------------+----------+

Report Cell Usage:
+------+----------------+------+
| |Cell |Count |
+------+----------------+------+
|1 |bd_0_hls_inst_0 | 1|
+------+----------------+------+

Report Instance Areas:
+------+---------+-------+------+
| |Instance |Module |Cells |
+------+---------+-------+------+
|1 |top | | 35|
|2 | bd_0_i |bd_0 | 35|
+------+---------+-------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 933.398 ; gain = 561.320
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 933.398 ; gain = 231.449
Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 933.398 ; gain = 561.320 dvbs2rate:solution1 22-Sep-2020, 3:56:18 PM
WARNING: [BD 5-236] No ports matched 'get_bd_ports -filter TYPE==clk'
Wrote : <H:\DVB-s2\dvbs2rate\solution1\impl\verilog\project.srcs\sources_1\bd\bd_0\bd_0.bd>
VHDL Output written to : H:/DVB-s2/dvbs2rate/solution1/impl/verilog/project.srcs/sources_1/bd/bd_0/synth/bd_0.v
VHDL Output written to : H:/DVB-s2/dvbs2rate/solution1/impl/verilog/project.srcs/sources_1/bd/bd_0/sim/bd_0.v
VHDL Output written to : H:/DVB-s2/dvbs2rate/solution1/impl/verilog/project.srcs/sources_1/bd/bd_0/hdl/bd_0_wrapper.v
Using BD top: bd_0_wrapper dvbs2rate:solution1 22-Sep-2020, 3:55:14 PM
WARNING: [IMPL 213-201] IO timing constraints are not applied without adding IO buffers.

Kindly guide me.

Waiting for your response.

Thank you.

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