08-24-2020 06:48 AM
I'm working on a transceiver using JESD204B with ZCU102 board. I have a working project that is using FMC0 and want to change connector to FMC1. It looks like a simple job and I think what has to be done is
1. Change JESD204 PHY IP core starting transceiver location. Initial project selects this as X1Y8 and using 8 lanes per link, this configuration is using bank 228 and 229 gth transceivers. New one selects this X0Y8 and this configuration is using bank 129 and 130 (I can confirm this in device after design is implemented.).
2. I change the other related pin locations (refclk, sysref, etc.), using ZCU102 schematic. For example refclk_p is connected to FMC0 D4, so I change the pin to connect FMC1 D4 pin. (G8 -> G27 on constraint file.)
As a result, I can't make the design work as expected. The ILA's I have placed are not seen in hardware manager (Due to refclk is not received I guess.) and since there is no refclk, JESD204 IP cores are not running. Other pins are seems working fine.
I checked the schematic and there is no difference between FMC0 and FMC1. Vivado implementation results are showing correct GTH transceivers are in use and clock is routed correctly. I don't know what can be the cause of this problem.
08-25-2020 12:50 PM
I am experiencing same problem. I am connecting ADS54J66 ADC to ZCU102. It works when connected to HPC1 but does not work when connected to HPC0. I am waiting for someone to respond to my post here https://forums.xilinx.com/t5/Serial-Transceivers/JESD-rx-sync-issue-on-ZCU102-HPC0/m-p/1143232
Are you connecting DAC or ADC to ZCU102 ?
08-25-2020 11:13 PM
I'm working on a TI transceiver with both ADC and DAC, my problem seems little different since I can't arm ILAs with possible reason of not receiving refclk. But it still doesn't make any sense since I changed refclk pin to exact same fmc pin as I mentioned in the previous post.