01-17-2020 06:29 AM - edited 01-17-2020 06:36 AM
I am going to preface by admitting that I know very little about DDR memory. I did a DDR3 design back in 2012 using the MIG core and that is my experience thus far.
Looking at the documentation here
The speed is noted as 2667Mbps. I am curious why the speed is such a low number considering that the DDR4 chip is capable of approximately 19GB/s? Is this the actual speed that the XCZU28DR-2FFVG1517E RFSoC can support?
I played with the MIG design a little and I setup the core to do 512bit rd/wr words and I was wondering if I could theoretically run at close to 10 to 15GB/s if my FPGA clock is 250MHz assuming proper clock domain crossing?
Thanks in advance.
01-18-2020 09:15 PM
Mbps = Mega bits per second (per data bit)
GB/s = Giga bytes per second
It is fairly easy to use compared to DDR3 MIG days. You'll probably want to use IPI, and let the interconnect handle any necessary clock domain crossings. I mention this as I am not sure if you know how much of the drudgery the tools are capable of doing now, compared to 2012.
01-21-2020 03:53 AM
Thanks for the response. The MIG tool is extremely easy to use I am finding, but the answer I was looking for has more to do with the speed that is advertised in the documentation. The 2667Mbps seems very slow to me for DDR4 memory. Maybe I am taking this number out of context or I am missing something. What is the actual speed(s) that the FPGA can handle for DDR4?
I noticed you said "per data bit" below, can I assume that the 2667Mbps is multiplied by the number of parallel bits on the memory interface?