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Observer
Observer
777 Views
Registered: ‎11-18-2019

Zynq-7000でマスターGP1のバースト長が16しかない

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日本語ですいません。

現在Vivado2018.3でxc7z020-1CLG400Qを使って設計をしていて

IPの” Zynq Prosessing System”からマスターポートGP0とGP1を出力しています。

アドレス範囲は0x4000から64KBと、0x8000から64KBです。

この設定でバースト長が4ビットしかなく、8ビットにしたいです。

実際に使用するアドレスは3KB分なので4KBのアドレス境界内です。

よろしくお願いします。

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Xilinx Employee
Xilinx Employee
701 Views
Registered: ‎11-05-2019

Hello,

 

Zynq M_AXI_GP Burst Length is up to 16.
Please check the same topic below and PG082.

https://forums.xilinx.com/t5/Processor-System-Design/About-the-burst-length-of-AXI4/td-p/520169

 


The first language of the forum is English.
Please post your questions in English so that the broader user community can help you.

 

Thanks,

Yoichi

View solution in original post

2 Replies
Xilinx Employee
Xilinx Employee
702 Views
Registered: ‎11-05-2019

Hello,

 

Zynq M_AXI_GP Burst Length is up to 16.
Please check the same topic below and PG082.

https://forums.xilinx.com/t5/Processor-System-Design/About-the-burst-length-of-AXI4/td-p/520169

 


The first language of the forum is English.
Please post your questions in English so that the broader user community can help you.

 

Thanks,

Yoichi

View solution in original post

Observer
Observer
684 Views
Registered: ‎11-18-2019

Thanks to you I was helped.

I'll do my best to ask questions in English.