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Participant 527114591@qq.com
Participant
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Registered: ‎10-15-2019

about IBUFGDS for ultrascale

please,  i can not find IBUFGDS for ultrascale in language templates in vivado 2018.3.

1.and what should i do if there is a pair of clock differential input signal and i need them to be a globle clock?(which doc should i look for?)

a solution: clk_p/clk_n ------>IBUFDS-------> BUFG------->MMCM?

2.there is another question that when i apply the solution: clk_p/clk_n ------>IBUFDS----------->MMCM, there are some errors which ask me to insert BUFG between I/O and MMCM, and i apply the solution: clk_p/clk_n ------>IBUFDS-------> BUFG------->MMCM,but there are some errors which, i think,  BUFG and MMCM may be placed in some same location.

 

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Registered: ‎01-22-2015

Re: about IBUFGDS for ultrascale

527114591@qq.com 

You are correct, there is no component called IBUFGDS for UltraScale devices.

When routing clocks from global clock (GC) pins to an MMCM, the preferred solution is:

clk_p/clk_n ------> IBUFDS-------> MMCM

since this solution uses a dedicated routing path from the FPGA-pins to the MMCM that maintains clock quality.

However, if your global clock pins are located in one of the special HD banks of UltraScale, then you must use the following sub-optimal solution:

clk_p/clk_n ------> IBUFDS-------> BUFG-------> MMCM

because, as described on page 10 of UG572(v1.9), the BUFG is needed for the IBUFDS to reach an MMCM.  Also for this situation, as described on page 10 of UG572, you should place a CLOCK_DEDICATED_ROUTE=FALSE constraint in the project .xdc constraints file to avoid a DRC error.

Mark

Guide avrumw
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Registered: ‎01-23-2009

Re: about IBUFGDS for ultrascale

markg@prosensing.com  is correct. But I just want to point out one thing.

There is not now, nor has there ever been a (real) primitive called and IBUFG (or IBUFGDS).

All inputs to the FPGA must go through an IBUF (single ended) or an IBUFDS (differential) (or an IOBUF/IOBUFDS) to get into the FPGA. The IBUF is the actual input buffer.

While an IBUF is an IBUF, some pin locations have special connections to the clocking resources - these have (variously) been named "GCLK", "GC", "CC" pins. These IBUFs at these locations are identical to other IBUFs, except that they have some extra dedicated routes available for clocking structures.

The nomenclature of the IBUFG was done (a long time ago) as a shorthand for "I want to instantiate an IBUF, and then want you to check that I have given it a PACKAGE_PIN/LOC location that is a GCLK/GC capable pin - if it isn't then issue an error and abort". That's all it is. You never need to instantiate an IBUFG - if you instantiate an IBUF and give it a PACKAGE_PIN/LOC location of a GCLK/GC/CC pin, then it has access to the extra routes, regardless of whether you instantated it as a IBUF or an IBUFG.

The nomenclature got confusing in some later technologies - was a "CC" pin (which is a regional clock capable pin" really appropriate for an IBUFG (since the G was to indicated "global clock"). In UltraScale, things get even more complicated with DBC/QBC pins - they are clocks, but are clearly not global clocks. So in UltraScale, Xilinx finally gave up and removed the IBUFG notation - simply use an IBUF and then place it to the proper place with a PACKAGE_PIN property.

Avrum

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Participant 527114591@qq.com
Participant
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Registered: ‎10-15-2019

Re: about IBUFGDS for ultrascale

thanks a lot. But my device is xcku040 belongs to Ultrascale in which there is no HD bank, however vivado forces me to add an BUFG. 

/*[Place 30-681] Sub-optimal placement for a global clock-capable IO pin and MMCM pair. As a workaround for this error, please insert a BUFG in between the IO and the MMCM.
ExtClk50M/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X1Y19
Ext50M_MMCM/inst/mmcme3_adv_inst (MMCME3_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME3_ADV_X0Y4

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
Ext50M_MMCM/inst/clkf_buf (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y98

Clock Rule: rule_mmcm_bufg
Status: PASS
Rule Description: A MMCM driving a BUFG must be placed in the same clock region of the device as the
BUFG
Ext50M_MMCM/inst/mmcme3_adv_inst (MMCME3_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME3_ADV_X0Y4
Ext50M_MMCM/inst/clkf_buf (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y98

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
Ext50M_MMCM/inst/clkout1_buf (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y97

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
and Ext50M_MMCM/inst/clkout2_buf (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y96

*/

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Participant 527114591@qq.com
Participant
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Registered: ‎10-15-2019

Re: about IBUFGDS for ultrascale

thanks a lot.

1.But my device is xcku040 belongs to Ultrascale in which there is no HD bank, however vivado forces me to add an BUFG. 

2. And I apply the solution(i do not make sure my understanding about your reply is correct): IBUF(a single-end clk input) ----> MMCM, there is an error below

/*[Place 30-681] Sub-optimal placement for a global clock-capable IO pin and MMCM pair. As a workaround for this error, please insert a BUFG in between the IO and the MMCM.
ExtClk50M/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X1Y19
Ext50M_MMCM/inst/mmcme3_adv_inst (MMCME3_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME3_ADV_X0Y4

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
Ext50M_MMCM/inst/clkf_buf (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y98

Clock Rule: rule_mmcm_bufg
Status: PASS
Rule Description: A MMCM driving a BUFG must be placed in the same clock region of the device as the
BUFG
Ext50M_MMCM/inst/mmcme3_adv_inst (MMCME3_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME3_ADV_X0Y4
Ext50M_MMCM/inst/clkf_buf (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y98

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
Ext50M_MMCM/inst/clkout1_buf (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y97

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
and Ext50M_MMCM/inst/clkout2_buf (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y96

*/

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Registered: ‎01-22-2015

Re: about IBUFGDS for ultrascale

527114591@qq.com 

Please ensure that the clock enters the FPGA on a global clock (GC) differential pin-pair.  For example, the following two pins from the xcku040sfva784 package file are a GC differential pin-pair:

AB26  IO_L12P_T1U_N10_GC_44     
AC26  IO_L12N_T1U_N11_GC_44 

For more information on pin definitions and package files for UltraScale devices, see UG575.

Also, try using the Clocking Wizard IP to setup the connection between the GC pin-pair and the MMCM - rather than instantiating IBUFDS and other components.

Mark

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