07-26-2020 12:55 AM
i have a fifo, it doesnot work, empty and full is both 1 from the begining. and when i give just one wr_en,overflow turns high at the same time,but the wr_count remains 0, it never serves as a counter from begining to the end. yes,i have a fifo_rst, but i didnot use it in the begining. and the simulation didinot run so far the time the fifo_rst asserts . on the other hand,i didnot give the fifo_rst a beginning value when initializing,but i set fifo_reset 0 when the module's rst asserts. please see the picture below.
wr_count remans 0 no matter i gave how many wr_en and wr_data. i had checked the whole schematic to ensure all connections are correct. wr_count is very import to me, i use it to trigger other signals.
what should i do?
by the way, this module is in a axi peropheral packaged ip.