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Visitor
Visitor
279 Views
Registered: ‎07-11-2020

asy fifo empty and full is pushed high at same time

i have a fifo, it doesnot work, empty and full is both 1 from the begining. and when i give just one wr_en,overflow turns high at the same time,but the wr_count remains 0, it never serves as a counter from begining to the end. yes,i have a fifo_rst, but i didnot use it in the begining. and the simulation didinot run so far the time the fifo_rst asserts . on the other hand,i didnot give the fifo_rst a beginning value when initializing,but i set fifo_reset 0 when the module's rst asserts. please see the picture below.

wr_count remans 0 no matter i gave how many wr_en and wr_data. i had checked the whole schematic to ensure all connections are correct. wr_count is very import to me, i use it to trigger other signals.

what should i do?

by the way, this module  is in a axi peropheral packaged ip.

 

微信图片_20200726154157.png微信图片_20200726154215.png微信图片_20200726154228.png11.png22.png

 

 

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Newbie
Newbie
222 Views
Registered: ‎08-03-2020

Hi,have you solved this problem? I meet the same problem and have no idea to solve it. Thanks for your help.
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Visitor
Visitor
189 Views
Registered: ‎07-11-2020

I delected rst of fifo, it worked in simulation but still wrong in ila, wr_counter keeps 0 all the time althouth it had been written in.

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