10-04-2020 04:35 PM
Hi, I used Vivado 2019.2 to create an asynchronous FIFO with read data count and write data count, the device I use is xcku3p, the read clock is 322Mhz and write clock is 325Mhz, the read is on when it's not empty, the write pauses when the FIFO has over 24 entries in it.
I expect the read_data_count and write_data_count to be equal or very close to each other when they are not equal. But from what I saw in Chipscope, they differ a lot. The data count shown in the snapshot is unsigned decimal.
How come read data count is less than write data count by around 7 ?
10-04-2020 05:36 PM
hello, email@example.com .
The full and empty signals don't de-assert at the same time.
The full signal de-asserts first, then the empty signal de-asserts.
So there are more write data written to the FIFO than the read data.
Check the full and empty signals' simulation wave, I think you'll notice it.
10-04-2020 09:55 PM - edited 10-04-2020 09:57 PM
Hi @zhangfeng , thanks for your reply. I ran a simulation, it matches what I saw in chipscope. The write data count leads read data count by around 8 in the simulation.
But I still cannot make sense of it. If the write data count shows the number of FIFO words in wr_clk domain, why is read data count off so much? What does read data count mean?
10-04-2020 10:34 PM
Data cannot be transferred directly when crossing clock domains,
usually such as Gray Code, 2FF Synchronizer are used to avoid metastability,
so Write/Read data count cannot be updated immediately likes Synchronous FIFO.
Because you're using a Asynchronous FIFO, no need to care write/read data count too much,
just care about the full/empty signals:
When the Asynchronous FIFO is not full, you can write;
When the Asynchronous FIFO is not empty, you can read.
10-04-2020 11:00 PM - edited 10-04-2020 11:01 PM
Hi @zhangfeng, I'm well aware of how asynchronous fifo works, while read data count may take a few cycles latency to show in the read clock domain after a burst of write because of the synchronization logic in the async fifo, it does not explain why the read data count stays at 2 in my simulation snapshot.(15/16 in my chipscope snapshot).
It should catch up to show the real number of FIFO words if there is delay, but it should not stay at 2.
In my code, I'm using read data count create some water marker signal and I'm using write data count to create an early full signal. I can use prog empty/prog full to do the same thing, I just don't get why read data count is not showing the real number of FIFO words (I assume write data count is correct here)
10-04-2020 11:51 PM
I think the reason is that you are reading the FIFO when writing.
According to the simulation wave you posted,
when wr_data_count is 0x07, the rd_data_count will change to 0x03 if rd_en is 0,
but the rd_en is 1, so rd_data_count is still 0x02.
wr_clk and rd_clk seems that they run at the same frequency,
so the rd_data_count keeps at 0x02, while writing/reading FIFO at the same time.