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664 Views
Registered: ‎08-07-2017

aurora xilinx ip instantiation problem with xilinx ise tool

hello sir, 

 I generated the core with Aurora 8B10B 5.2, 1 lanes, lane width 2, Line rate 3.125 Gbps, GT refclk 156.25 Hhz, Duplex, Framing and no flow control, in Xilinx ISE 13.2 version. after generation of HDL code of Aurora ip and instantiat wrapper in top design module. but when i run sysnthesis it gives error 

ERROR: Core Generator generated file aurora_1/src/aurora_1.vhd was not found.
ERROR: Core Generator generated file aurora_1/src/aurora_1.vhd was not found.
ERROR: Core Generator generated file aurora_1/src/aurora_1.vhd was not found.
ERROR: Unable to find top-level HDL source file for core: aurora_1.

thanks 

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3 Replies
nmanitri
Xilinx Employee
Xilinx Employee
630 Views
Registered: ‎06-13-2018

Hello arvind@dandotiya,

Can you please let me know the following details:

1. Which device you are targetting?

2. Did you try with ISE 14.7? If no, Please try in ISE 14.7 and share the results with us.

Regards,

Naveen

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csattar
Moderator
Moderator
604 Views
Registered: ‎05-02-2017

hi arvind@dandotiya ,

 

can you please let me know the steps you have followed to create the design .

Regards
Chandra sekhar
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csattar
Moderator
Moderator
577 Views
Registered: ‎05-02-2017

hi arvind@dandotiya ,

 

can you please let us know the update and as well as the is this issue is sloved ?

 

 

Regards
Chandra sekhar
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