05-29-2020 07:17 AM - edited 05-29-2020 08:25 AM
Below is my Block design for 1 axi_Interconnect core connected to 2 ddr4_sdram cores. During the IP Packager stage, I get the message that "ASSOCIATED_BUSIF bus parameter is missing on differential reference clock to ddr4 controller"
Any ideas how to fix this warning message? I tried modifying the properties for this clock signal as shown below, but there's no ASSOCIATED_BUFIF property to associate the clock to.
05-29-2020 12:11 PM
I tried connecting the differenential DDR4 reference clock separately before exporting the port... it changes the messages from IP packager, but still complains that ASSOCIATED_BUFIF is missing...
06-03-2020 04:40 AM - edited 06-03-2020 04:49 AM
I tried something similar at my end and couldn't reproduce the exact warnings with 2019.2. However, in this specific scenario it looks it is safe to ignore them . Please refer ASSOCIATED_BUSIF section from this UG