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FPGADude99
Visitor
Visitor
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Registered: ‎04-29-2020

axi_Interconnect + 2 ddr4_sdram: ASSOCIATED_BUSIF bus parameter is missing on differential reference clock to ddr4 controller...

Below is my Block design for 1 axi_Interconnect core connected to 2 ddr4_sdram cores.  During the IP Packager stage, I get the message that "ASSOCIATED_BUSIF bus parameter is missing on differential reference clock to ddr4 controller"

Any ideas how to fix this warning message?  I tried modifying the properties for this clock signal as shown below, but there's no ASSOCIATED_BUFIF property to associate the clock to.

associated_bufif_on_differential_clock_made_external_to_bd.png

associated_bufif_on_differential_clock_made_external_to_bd_page2.png

 

ddr4_orca.png

ddr4_address_map.png

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FPGADude99
Visitor
Visitor
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Registered: ‎04-29-2020

I tried connecting the differenential DDR4 reference clock separately before exporting the port... it changes the messages from IP packager, but still complains that ASSOCIATED_BUFIF is missing...

 

tmp.png 

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vsrunga
Xilinx Employee
Xilinx Employee
326 Views
Registered: ‎07-11-2011

Hi, 

I tried something similar at my end and couldn't reproduce the exact warnings with 2019.2. However, in this specific scenario it looks it is safe to ignore them . Please refer ASSOCIATED_BUSIF section from this UG 

 

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