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Contributor
Contributor
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Registered: ‎12-20-2011

axi chip2chip with 4 lanes GTH

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Hi, we have a board with 4-lane GTH, and we try to  communicate with another board through an axi-chip2chip IP. However, the axi-chip2chip IP only support 128-bit AXI with 2 lanes. is it possible to fully use the 4-lane GTH with 256-bit AXI by instantiating two axi-chip2chip IPs ? if that is possible, is there anything I should pay attention to?

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @fanxitian 

1. No, that is not possible to use 256-bit.
This IP only support 32/64/128 bit due to data-packing algorithm that CHIP2CHIP IP implemented.
You have to add additional IP to convert this data width. (For example AXI Data Width Converter from Infrastucture cores. See also PG059 )
C2C_intro.png

2. If you use two instances of AXI CHIP2CHIP, each instance will work independently.
These module will not match your usecase requirement


3. Aurora lanes number used is decided by AXI CHIP2CHIP IP configuration. ( some will need 2/4/6 and other ). This is not user selectable.
C2C_GUI.png

Regards
Leo

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Xilinx Employee
Xilinx Employee
305 Views
Registered: ‎03-30-2016

Hello @fanxitian 

1. No, that is not possible to use 256-bit.
This IP only support 32/64/128 bit due to data-packing algorithm that CHIP2CHIP IP implemented.
You have to add additional IP to convert this data width. (For example AXI Data Width Converter from Infrastucture cores. See also PG059 )
C2C_intro.png

2. If you use two instances of AXI CHIP2CHIP, each instance will work independently.
These module will not match your usecase requirement


3. Aurora lanes number used is decided by AXI CHIP2CHIP IP configuration. ( some will need 2/4/6 and other ). This is not user selectable.
C2C_GUI.png

Regards
Leo

View solution in original post

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