06-24-2019 07:37 AM
How to configure the BRAM for bit wise write. i want to generate a blk_mem 32 width and 32 depth with bit write enable. Please can any one help on this ?
Any help or suggestions are highly appreciated.
I did not get much info related to wea signal in the BRAM, am confusing with the signal, please Can any one elaborate it more like
1) exactly what is the use of it ?
2) what is the max size it will support ?
3) how to configure it ?
06-24-2019 08:33 AM
Bit wise writing is not supported , Byte wise writing is supported. There is Byte wide write enable signal for this.
When used as SDP memory, the WEBWE[7:0] port is the byte-write enable. When used as TDP memory, the WEA[3:0] and WEB[3:0] are byte-write enables for port A and port B, respectively.
There is section for this in the user guide 573 on page no 49. You need to follow this rule
06-24-2019 05:47 PM
As @pthakare said, the block RAMs don't have bit enables - only byte (or 9-bit if parity is used) enables are provided.
However, for a 32x32 RAM, you can use distributed RAM instead. If you needed a 32x32 dual port RAM this would take 64 LUTs, which is pretty small. The distributed RAMs are each inherently 64x1 SRAMs (you use two for dual port RAMs) - so each bit of the RAM is independently implemented, including having a separate WE for each RAM (hence each bit).
Thus with 64 LUTs you can built a 32x32 (actually 64x32) true dual port RAM with bit enables. Note: ditributed RAMs are 0 clock latency (combinatorial) reads - if you want a 1 clock latency read (like RAMB cells) then you need to use a flip-flop after the distributed RAM - there is a dedicated connection in the CLB for the output of the distributed RAM to the flip-flop.
06-24-2019 11:12 PM
I generated distributed RAM, but still it showing wea as 1 bit and there is no controll option in the GUI for wea. Can you please help on this ?
06-25-2019 03:17 AM