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rutabagazuma
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Registered: ‎04-02-2019

cant access AXI DMA controller registers from PS

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I am running a simulation which I have added an AXI DMA v7.1.   I am trying to perform AXI read and write cycles mastered by the AXI VIP.   My read and write cycles complete, but registers with known set bits (MM2S_DMACR; offset 0x00, bit 1) reads as zero and attempts to write (MM2S_SA; offset 0x18) a non zero value always returns zero when read.

I have a larger design with many DMA controllers which displays the same behavior.  I am trying to dig into the root cause and have added a single DMA controller to simulate.

What would cause the registers to be inaccessible but the AXI interface to operate correctly?

dmacircuit.png
waves.png
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rutabagazuma
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Registered: ‎04-02-2019

I figured it out.  I was attempting to read MM2S registers when I had disabled that function in the core creation.  S2MM configuration registers appear to work fine.

View solution in original post

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patocarr
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Registered: ‎01-28-2008
TKEEP should be tied high.

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

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rutabagazuma
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Registered: ‎04-02-2019
thanks for the feedback but holding s_axis_s2mm_tkeep[3:0] high did not resolve my issue with the s_axi_lite register access issue
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dgisselq
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Registered: ‎05-21-2015

@rutabagazuma,

I can think of a couple of possibilities.

  1. You haven't shown the WSTRB signal.  If this signal is all zeros, nothing will change in spite of any writes
  2. I'm not sure where you've tapped the AXI-lite port from.  Your tap should be from the wires going into the DMA, not on the other side of the interconnect.  If you tap the wrong wires, you might see a transaction that never went to the DMA core
  3. It's also possible you are addressing the wrong device, or the wrong address for the register in question.

These are just my few thoughts based upon the information you've shown.

Dan

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rutabagazuma
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Registered: ‎04-02-2019

Dan, thanks for the feedback on my issue.

Confirmed that my wave capture is of the signals going into the DMA.

WRT the wstrb, I believe the DMA implementation of the  axi-lite protocol does not support it.  From the AXI DMA doc v7.1:

Note: The AXI4-Lite write access register is updated by the 32-bit AXI Write Data (*_wdata) signal,and is not impacted by the AXI Write Data Strobe (*_wstrb) signal. For a Write, both the AXI Write Address Valid (*_awvalid) and AXI Write Data Valid (*_wvalid) signals should be asserted together.

 

I am fairly confident of the offset and base address of the IP, at least as far as the data sheet can confirm.

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dgisselq
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Registered: ‎05-21-2015

@rutabagazuma,

If you replace the DMA with your own AXI-lite peripheral, does it work?

Dan

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rutabagazuma
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Registered: ‎04-02-2019

I figured it out.  I was attempting to read MM2S registers when I had disabled that function in the core creation.  S2MM configuration registers appear to work fine.

View solution in original post

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