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k.e.elsayed
Visitor
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13,923 Views
Registered: ‎11-14-2013

change in coe file

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I have a question about xilinx ise memory IP cores.
I use a .coe file to initialize the contents of the memory by selecting it during the IP core generator wizard, When i change the contents of the .coe file I have to re-generate the core for the changes to take effect which is a time consuming process, is there another way ?

 

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vsrunga
Xilinx Employee
Xilinx Employee
21,316 Views
Registered: ‎07-11-2011

Hi,

 

In simulation you can hand edit the .mif file which is a binary file generated by .coe file and will be available in IP_core directory, in hardware you can go for data2mem conecept details of which are explained in the  below pdf.

 

http://www.xilinx.com/Attachment/Xilinx_Answer_46945_Data2Mem_Usage_and_Debugging_Guide.pdf

 

 

 

Hope this helps.

 

 

Regards,

Vanitha.

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vsrunga
Xilinx Employee
Xilinx Employee
21,317 Views
Registered: ‎07-11-2011

Hi,

 

In simulation you can hand edit the .mif file which is a binary file generated by .coe file and will be available in IP_core directory, in hardware you can go for data2mem conecept details of which are explained in the  below pdf.

 

http://www.xilinx.com/Attachment/Xilinx_Answer_46945_Data2Mem_Usage_and_Debugging_Guide.pdf

 

 

 

Hope this helps.

 

 

Regards,

Vanitha.

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Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

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k.e.elsayed
Visitor
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13,882 Views
Registered: ‎11-14-2013

That worked 
Thank you

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balkris
Xilinx Employee
Xilinx Employee
13,616 Views
Registered: ‎08-01-2008
The manual modification expected to work however not recommended to use. The reason is when you regenerate the core it will again update the mif file. I think better way to change the coe file and regenerate the core again. Hope it will help
Thanks and Regards
Balkrishan
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emmettbradford
Explorer
Explorer
6,436 Views
Registered: ‎04-23-2013

I generated a true dual port 16-1024 RAM.

I initialized with a COE.

A MIF was generated correctly.

Now changes to the COE do not update the MIF.

When I try to re-generate the core, it says all output products are up to date.

 

How do I effect the COE changes to the MIF and the core?

 

I am using Vivado 2016.2, on Win 10 64bit.

blk_mem_gen_v8_3_3

 

Thanks,

Emmett

 

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balkris
Xilinx Employee
Xilinx Employee
6,432 Views
Registered: ‎08-01-2008
you can reset the output product and regenerate the core . right click on core name --> reset output products

Thanks and Regards
Balkrishan
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emmettbradford
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Explorer
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Registered: ‎04-23-2013

That worked.

Thanks.

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