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Explorer
Explorer
276 Views
Registered: ‎01-04-2013

dds compiler 6.0实现相位位宽64位

大家好,请问怎么用dds compiler实现64位相位输出呢?

QQ拼音截图20200210112647.png

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Adventurer
Adventurer
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Registered: ‎09-21-2019

Re: dds compiler 6.0实现相位位宽64位

@danpianji88 You can not take it more than 48.

There is a formula in documentation to calculate the phase width.please go through the documention of DDS compiler.

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Explorer
Explorer
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Registered: ‎01-04-2013

Re: dds compiler 6.0实现相位位宽64位

感谢回复 请问如果用Verilog自己实现一个相位位宽为64位的DDS,如何确定相位幅度转换器(ROM)的地址位宽呢?也就是说如何做相位截断呢?
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Adventurer
Adventurer
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Registered: ‎09-21-2019

Re: dds compiler 6.0实现相位位宽64位

@danpianji88 Can you please translate it into english?

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Explorer
Explorer
171 Views
Registered: ‎01-04-2013

Re: dds compiler 6.0实现相位位宽64位

Hello, Thanks for your replying

I'm using dds compiler 6.0 ,I configure the phase width to 48bit,can you tell me what the depth of sine lut

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Adventurer
Adventurer
106 Views
Registered: ‎09-21-2019

Re: dds compiler 6.0实现相位位宽64位

you can take depth as you wish.

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