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269 Views
Registered: ‎12-04-2019

dds_compiler_v6_0_12

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I need to simulate a customer design which include a dds module which has this:


LIBRARY dds_compiler_v6_0_12;
USE dds_compiler_v6_0_12.dds_compiler_v6_0_12;

Where can I find/generate this library?

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212 Views
Registered: ‎06-21-2017

Re: dds_compiler_v6_0_12

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The file in question is for simulation only and is created when you customize the DDS from the IP GUI.  It is merely a wrapper for the dds sim model supplied by Xilinx and puts the GUI selected parameters into the generics for the sim model.  Vivado will include it in your simulation sources.

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Teacher drjohnsmith
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Registered: ‎07-09-2009

Re: dds_compiler_v6_0_12

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you need to talk to who ever supplied the code you have as it could be from anywhere. Thats the point of libraries.

Xilinx have a dds compiler, built int which ever tool your using ,
but if the library is defined like this , it would be unusual for a Xilinx design,


What tool chain and which chip you using,


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235 Views
Registered: ‎12-04-2019

Re: dds_compiler_v6_0_12

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The module is generated with Xilinx Vivado 2016.1:

....
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--

-- DO NOT MODIFY THIS FILE.

-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
-- IP Revision: 12

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

LIBRARY dds_compiler_v6_0_12;
USE dds_compiler_v6_0_12.dds_compiler_v6_0_12;

ENTITY dds_test_2 IS
PORT (
aclk : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_phase_tvalid : OUT STD_LOGIC;
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END dds_test_2;
....

What I'm searching for is the dds_compiler_v6_0_12 library.
The part is a xc7k325tfbg676-1

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231 Views
Registered: ‎06-21-2017

Re: dds_compiler_v6_0_12

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What Vivado version are you using?  The simulation model in 2019.1 has these lines:

LIBRARY dds_compiler_v6_0_18;
USE dds_compiler_v6_0_18.dds_compiler_v6_0_18;

You could try to change the lines

LIBRARY dds_compiler_v6_0_12;
USE dds_compiler_v6_0_12.dds_compiler_v6_0_12;

to whatever library version that your version of Vivado includes.  The DDS compiler hasn't changed much for a long time, it might work.

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Teacher drjohnsmith
Teacher
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Registered: ‎07-09-2009

Re: dds_compiler_v6_0_12

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What do you know about Xilinx IP ?

what you have there is a Xilinx IP block,
you would not normaly include this vhdl file in vivado, but the xci file that's generated when you make the DDS IP in vivado.

Taking step back,
your importing from ISE into Vivado I seem to remember,

Do you have the original ISE project ?
you can open that in Vivado , and that should have imported all the bits you need.

If you only have the VHDL files, then you might want to try creating a DDS IP core in Vivado, that is assuming you know how it was configured ?

Else wise, I'd suggest you re run the old ISE, and ensure you have the ISE project file,

Are you aware of this

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug911-vivado-migration.pdf
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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213 Views
Registered: ‎06-21-2017

Re: dds_compiler_v6_0_12

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The file in question is for simulation only and is created when you customize the DDS from the IP GUI.  It is merely a wrapper for the dds sim model supplied by Xilinx and puts the GUI selected parameters into the generics for the sim model.  Vivado will include it in your simulation sources.

View solution in original post

196 Views
Registered: ‎12-04-2019

Re: dds_compiler_v6_0_12

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Thanks. I found the dds_compiler_v6_0.vhd in one of the customers archives, will try that
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