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Visitor mawnash
Visitor
191 Views
Registered: ‎08-02-2018

frequency generation for uart

Hi,

I need to generate 1.8432mhz frequency with respect to 125mhz clock for uart to get the 115.2k baud rate using Xilinx ip. Does anyone have suggestions?please let me now.

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Xilinx Employee
Xilinx Employee
177 Views
Registered: ‎11-30-2007

Re: frequency generation for uart

UART usually requires a 16x oversampling clock - that is in your case the 1.8432 MHz.

And UARTs have a +-5% limit usually that will be accepted for the frequency.

125 MHz / 1.8432 = 67.8 ==> This would be your divider.

 

Solution: use a PLL that can generate only fixed point - and pick the 68 as divider factor.

Then the resulting frequency for the UART would be:

125/68/16 = 114.889 kHz.

This is 99.7 % of the target frequency and well inside the +-5 % limit.

 

Will work without any issues.

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Visitor mawnash
Visitor
168 Views
Registered: ‎08-02-2018

Re: frequency generation for uart

It looks good but it won't generate exact 1.8432mhz in my case software is setting this frequency as exact value.

so I thought of creating 184.32mhz clk with 125mhz clock as the primary clock and use 100 as divider value to get exact 1.8432mhz.

will cause any hold or setup violations?

Is this possible? what is your comments?

 

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Xilinx Employee
Xilinx Employee
157 Views
Registered: ‎11-30-2007

Re: frequency generation for uart

PLLs have fixed multiply/divide factors.

And they have a lower and upper value for the VCI frequency that has to be respected.

Depending on the device these values can differ.

FPGAs have PLLs and MMCMs inside the fabric, Zynq based devices have PLL inside the PS-subsystem and PLLs and MMCMs inside programmable logic.

e.g. Artix-7 Devices have spec'ed the VCO min = 800 MHz, while max VCOI frequency in -1 speedgrade is 1600 MHz.

With a input clock of 125 MHz you can e.g. use:

Fvco = Fclkin * M / D

Fout = Fvco / divider_out_value

 

Note that you might not directly create the target frequency of 1.8432 MHz out of a PLL - due to the restriction of Fvco_min - and the size of the dividers.

Usually UARTs have their own prescaler and accept even larger input frequencies.

 

Anyhow - my recommendation would be to use the clocking wizards (either for PL fabric in FPGA or the PS-wizard for the PS-System in Zynq based devcies) - they usually try to come as close as possible to the target frequencies.

 

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