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Adventurer
Adventurer
14,014 Views
Registered: ‎02-11-2014

ipcore block RAM- verilog code

Hi,

Below provided is the verilog code for using block ram . My aim is : I want to write to block ram when "input Write" is high. And I want to read when "input RD" is high. 

 

During simulation , I tried to read data from a particular address, and I am getting result. But the write operation is not working,I cannot see the data in MIF file.  While writing data to block ram , data should write in the MIF file right??  

Can you please have a look, and let me know where I did wrong?

 

 

module Datamemory_BRAM(output reg[15:0] Rdata,input[15:0] data_add,Wdata, input Write,RD,CLK);
wire[15:0] out;
wire[12:0] addra; 
assign addra=data_add[12:0];  // just need first 13 bit to address my memory location
DRAM mem (
.clka(CLK), // input clka
.wea(Write), // input [0 : 0] wea
.addra(addra), // input [12 : 0] addra
.dina(Wdata), // input [15 : 0] dina
.douta(out) // output [15 : 0] douta
);

always@(posedge CLK)
begin
if(RD==1)
Rdata=out;
end
endmodule

isim-blockram.JPG
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8 Replies
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Xilinx Employee
Xilinx Employee
14,008 Views
Registered: ‎07-11-2011

Hi,

 

Why is your CLK always '1'  or you have not captured the toggling?

 

It looks like you have instantiated DRAM, is it your own code? How  did you initialize your memory?

Do you use available Block memory generator IP?

 

Please go through below PG058 for detailed explanation and example design and test bench,

If you initialzed the memory correctly , used proper clocking and it won't work please uoload your core .xci and .coe for investigation

http://www.xilinx.com/support/documentation/ip_documentation/blk_mem_gen/v8_2/pg058-blk-mem-gen.pdf

 

 

Regards,

Vanitha

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Xilinx Employee
Xilinx Employee
13,993 Views
Registered: ‎08-01-2008

It seems inputs are not drive correctly. I would recommend to use block memory Generator .

You can use example design provided with the Block memory generator core
Thanks and Regards
Balkrishan
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Adventurer
Adventurer
13,961 Views
Registered: ‎02-11-2014

Hi Vanitha,

I initilazed block memory generator inside the main program. I went through the user guide before designed my block ram. I agin had a look on the user guide but still now it is not working. To makesure that the problem is with the clock, I tested the code using FPGA also. Can you please help me, can you have a look on it? Attached is the .ceo and coe file. 

 

module Datamemory_BRAM(output reg[15:0] Rdata,input[15:0] data_add,Wdata,
input Write,RD,CLK);
wire[15:0] out;
wire[12:0] addra;
assign addra=data_add[12:0];
DRAM mem ( 
.clka(CLK), // input clka
.wea(Write), // input [0 : 0] wea
.addra(addra), // input [12 : 0] addra
.dina(Wdata), // input [15 : 0] dina
.douta(out) // output [15 : 0] douta
);

always@(posedge CLK)
begin
if(RD==1)
Rdata=out;
end
endmodule

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Adventurer
Adventurer
13,960 Views
Registered: ‎02-11-2014

Hey,

I have a quick question too, If the write operation is performing correctly, the data should write on .coe file or .mif file? 

thanks

kathy

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Xilinx Employee
Xilinx Employee
13,943 Views
Registered: ‎07-11-2011

Hi,

 

I  am assuming your question should be " If the write operation is to be performed correctly, the data should write on .coe file or .mif file?"

We always recommend to use .coe, .mif will be generated by the core and will be used in simulation but the source is .coe

 

I noticed that you did two posts and one of them had .xco and .coe attached.

Your memory deepth seems to be 6553 but your .coe has only 6 entries so I suspect if IP is considering it as idelaly .coe should have full depth initilized.

Eventhough IP considered your .coe, initialized 6 locations are all zeros

So it is obvious that you will get zero data from BRAM

 

Another observation is your configuration seems to be single port RAM and in your first post you wrote "My aim is : I want to write to block ram when "input Write" is high. And I want to read when "input RD" is high"

If that is the case you need to have simple dual port RAM which generates write enable and read enable where as single port RAM will have only write enable

 

Hope this helps

 

Regards,

Vanitha

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Adventurer
Adventurer
13,923 Views
Registered: ‎02-11-2014

Thanks a lot for your valuable suggestions and comments. As u said for my application the block ram should be simple dual port. For the .coe file, during block ram core generation I set  to fill the remaining locations with zero. 

 

I changed my block ram to simple dualport, and tested my code in FPGA and using LCD toavoid any clocking issues.  Following procedures i did

1) I gave all inputs in my program itself , where 

data_add=16'b0000_0000_0000_0000; //address to write
Wdata=16'b0000_0000_0000_0110; //data

RD=1;//read enable

WD=1;//write enable

2)I noticed that the  output read data in port B  is 16'b0000_0000_0000_0110; BUT when I looked to.coe file data is not written over there. So my question is when we write to block RAM, if the write operation is performing correct then that data should be in .coe file??

 

In my application, I want to save my write data  for further process. 

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Xilinx Employee
Xilinx Employee
13,913 Views
Registered: ‎07-11-2011

Hi,

 

Glad that you are able to read from RAM

 

The content in .coe file is just initial data, if you write into RAM asserting write enable and set Wdata=16'b0000_0000_0000_0110; then initial data will be replaced.

BRAM is volatitle, unles you swtich of the FPGA power your written data will be stored in it and can be used for further processing, but when you initialize it using .coe when ever you switch off and on the board and you have not written new data .coe contents can be read.

 

Hope this clarifies

 

Regards,

Vanitha

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Newbie
Newbie
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Registered: ‎02-26-2015

Hii currently I am working on writing and reading data from dual port ram by instantiating it in the Ip core. Can you send me the program and test bench for taht. thyank you.

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