and also i'm implementing jesd204b interface between adc(tx) and fpga(rx) as subclass1(config : continuous mode)
In my jesd configuration factors, F is 1 and K is 32. and using 4 lanes(lane 0 ~ lane 3)
So, multi-frame size, the MF is 32 and TW maximum value is 24(32-8) and minimum value is 8. the range is 8 ~ 24.
my configuration for subclass1 is that sysref low to high transition is captured in adc and fpga at system clock's falling edge.
after jesd link-up(rx sync high), when i read the jesd ip register about buffer adjust for each lane(0x830,0x870,0x8B0,0x8F0 for lane0 ~ lane3), if each read value(buffer adjust) or the smallest value is in the range of TW range(8~24), does it mean that i get deterministic and repeatable latency from adc to fpga by jesd204b subclass1 perfectly?
To get this value in proper range, I can change the LMFC phase offset in ADC(tx).
For safety with deterministic and repeatable latency, do i have to read the buffer adjust register always(monitoring the buffer adjust)? if the value is not proper(value is changing or out of range, do i have to reset?