cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
wrwadley
Visitor
Visitor
10,463 Views
Registered: ‎10-20-2009

multiplier rdy signal?

Hello!

 

I am using the LogicCore Multiplier v11.0, and I am wondering what is the best way to know when the operation is completed.

 

There is no "rdy" signal that I can use. I suppose that I should either check that the product output is not zero, or wait a predefined number of clock cycles (based on the pipelining?).

 

What is the best way to handle this?

 

Thank you very much.

 

Bill

Tags (3)
0 Kudos
2 Replies
gszakacs
Instructor
Instructor
10,462 Views
Registered: ‎08-14-2007

Multiplier cores generally have a fixed pipeline delay.  This can vary depending on the

core parameters, but should either be shown in the last page of the CoreGen customization

or in the core datasheet.  If you have trouble finding the correct number of clocks to

match the core pipeline delay I would suggest simulating the core with a simple testbench

to see when the outputs change in simulation relative to the inputs.  If you have an

input valid signal you can delay it by the appropriate number of clock cycles to have

an output valid from the multiplier core.

 

HTH,

Gabor

-- Gabor
wrwadley
Visitor
Visitor
10,456 Views
Registered: ‎10-20-2009

Thank you!

 

In my current testbench (where I discovered the delay), I see that it takes 5 clocks to get to the result. I also happen to have the multiplier configured with 5 pipelining stages. That, I believe, explains the 5 clocks. However, it is very nice to hear it from someone else that knows what they are doing.

 

Kudos to you!

 

Bill

0 Kudos