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awoz92gmu
Observer
Observer
525 Views
Registered: ‎11-26-2018

"Full" and "Empty" thresholds for cascaded FIFO36E2s

I'm cascading 4 FIFO36E2s together. The larger FIFO I'm forming has 9-bit wide data, and 16K locations which requires 4 FIFO36E2s cascaded together. 

What I'm not sure about is when the 16K locations is split between the 4 FIFOs what would the generics for the programmable full and empty thresholds be set to on each of the 4 FIFOs (PROG_EMPTY_THRESH , PROG_FULL_THRESH) ? 

 

component FIFO36E2
generic (
CASCADE_ORDER : string := "NONE";
CLOCK_DOMAINS : string := "COMMON";
EN_ECC_PIPE : string := "FALSE";
EN_ECC_READ : string := "FALSE";
EN_ECC_WRITE : string := "FALSE";
FIRST_WORD_FALL_THROUGH : string := "FALSE";
INIT : std_logic_vector (71 downto 0) := X"000000000000000000";
IS_RDCLK_INVERTED : bit := '0';
IS_RDEN_INVERTED : bit := '0';
IS_RSTREG_INVERTED : bit := '0';
IS_RST_INVERTED : bit := '0';
IS_WRCLK_INVERTED : bit := '0';
IS_WREN_INVERTED : bit := '0';
PROG_EMPTY_THRESH : integer := 256;
PROG_FULL_THRESH : integer := 256;
RDCOUNT_TYPE : string := "RAW_PNTR";
READ_WIDTH : integer := 4;
REGISTER_MODE : string := "UNREGISTERED";
RSTREG_PRIORITY : string := "RSTREG";
SLEEP_ASYNC : string := "FALSE";
SRVAL : std_logic_vector (71 downto 0) := X"000000000000000000";
WRCOUNT_TYPE : string := "RAW_PNTR";
WRITE_WIDTH : integer := 4
);
port (
--Cascade Signals outputs: Multi-FIFO cascade signals
CASDOUT : out std_logic_vector(63 downto 0);
CASDOUTP : out std_logic_vector(7 downto 0);
CASNXTEMPTY : out std_ulogic;
CASPRVRDEN : out std_ulogic;
DBITERR : out std_ulogic;
--Read Data outputs: Read output data
DOUT : out std_logic_vector(63 downto 0);
DOUTP : out std_logic_vector(7 downto 0);
ECCPARITY : out std_logic_vector(7 downto 0);
--Status outputs: Flags and other FIFO status outputs
EMPTY : out std_ulogic;
FULL : out std_ulogic;
PROGEMPTY : out std_ulogic;
PROGFULL : out std_ulogic;
RDCOUNT : out std_logic_vector(13 downto 0);
RDERR : out std_ulogic;
RDRSTBUSY : out std_ulogic;
SBITERR : out std_ulogic;
WRCOUNT : out std_logic_vector(13 downto 0);
WRERR : out std_ulogic;
WRRSTBUSY : out std_ulogic;
--Cascade Signals inputs: Multi-FIFO cascade signals
CASDIN : in std_logic_vector(63 downto 0);
CASDINP : in std_logic_vector(7 downto 0);
CASDOMUX : in std_ulogic;
CASDOMUXEN : in std_ulogic;
CASNXTRDEN : in std_ulogic;
CASOREGIMUX : in std_ulogic;
CASOREGIMUXEN : in std_ulogic;
CASPRVEMPTY : in std_ulogic;
--Write Data inputs: Write input data
DIN : in std_logic_vector(63 downto 0);
DINP : in std_logic_vector(7 downto 0);
INJECTDBITERR : in std_ulogic;
INJECTSBITERR : in std_ulogic;
--Read Control Signals inputs: Read clock, enable and reset input signals
RDCLK : in std_ulogic;
RDEN : in std_ulogic;
REGCE : in std_ulogic;
RSTREG : in std_ulogic;
SLEEP : in std_ulogic;
--Write Control Signals inputs: Write clock and enable input signals
RST : in std_ulogic;
WRCLK : in std_ulogic;
WREN : in std_ulogic
);
end component FIFO36E2;

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drjohnsmith
Teacher
Teacher
519 Views
Registered: ‎07-09-2009

can I suggets, cascading fifos yourself is a fun exercise, but ,dont do it.

Use the Xilinx IP generator.

IP catalog on left hand side of Vivado

then Memories and storage elements -> FIFOs -> FIFO generator

Out of interest, the tools default  for a 16 K fifo to the folowing

full threshold assert at 16380

full threshold negate at 16379

 

empty threshold assert at 2

empty threshold negate at 3

 

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