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Visitor
Visitor
366 Views
Registered: ‎08-27-2018

read or write BRAM error

I find that there are always read or write errors when i am working on the project  for me  xczu19eg boards.So i guess that there are hardware problems.

Then i instantiate the Block memory generator IP and connect it with VIO IP.

微信图片_20200304150307.png微信图片_20200304150315.png

 

Does this indicate BRAM damage?I have several similar boards.

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Adventurer
Adventurer
310 Views
Registered: ‎05-30-2017

Hi Michael,
It is difficult to know the answer to your question from the information you provided. Can you attach the RTL? Also, can you include all BRAM signals in your ILA and recapture? It would be very important to include the write enables, port enables, and resets. Lastly, we will need to see how your BRAM is configured.
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Visitor
Visitor
283 Views
Registered: ‎08-27-2018

Hi,

Thanks for your reply.

Here is my rtl.

 

module Bram_test(
input clk_n,
input clk_p
);

//parameter data_width=1152;
//parameter data_width=1024;
//parameter addr_deep=3;

logic clk;
logic clk_50;


IBUFDS u_ibuf (.I(clk_p), .IB(clk_n), .O(clk));

clk_wiz_0 u_clk_50(
.clk_in1 (clk),
.reset (1'b0),
.clk_out1 (clk_50),
.locked ()
);


(*DONT_TOUCH = "TRUE"*)logic [15:0] dbiterr;
(*DONT_TOUCH = "TRUE"*)logic [15:0] sbiterr;
(*DONT_TOUCH = "TRUE"*)logic [15:0] rdaddrecc;
logic [1023:0] rdata ;


logic rd_en;
logic enbwren;
logic [15:0] injectdbiterr;
logic [15:0] injectsbiterr;
logic [1023:0] wdata;
logic [14:0] raddr;
logic [14:0] waddr;


genvar bb;
generate

for (bb = 0; bb < 16; bb = bb + 1)
begin: ram_test

RAMB36E2 # (
//.RDADDR_COLLISION_HWCONFIG ("PERFORMANCE"),
.SIM_COLLISION_CHECK ("ALL" ),
//.DOA_REG (1 ),
//.DOB_REG (1 ),
.DOA_REG (0 ),
.DOB_REG (0 ),
.EN_ECC_READ ("TRUE" ),
.EN_ECC_WRITE ("TRUE" ),
.INIT_A (36'h000000000),
.INIT_B (36'h000000000),
.INIT_FILE ("NONE" ),
//.RAM_MODE ("SDP" ),
//.RAM_EXTENSION_A ("NONE" ),
//.RAM_EXTENSION_B ("NONE" ),
.READ_WIDTH_A (72 ), // 0-72
.READ_WIDTH_B (0 ), // 0-36
.WRITE_WIDTH_A (0 ), // 0-36
.WRITE_WIDTH_B (72 ), // 0-72
.RSTREG_PRIORITY_A ("RSTREG" ),
.RSTREG_PRIORITY_B ("RSTREG" ),
.SRVAL_A (36'h000000000),
.SRVAL_B (36'h000000000),
.WRITE_MODE_A ("Read_First"),
.WRITE_MODE_B ("Read_First")
)

uram (

//ECC Signals
.DBITERR ( dbiterr[bb] ),
.ECCPARITY ( ),
.ECCPIPECE (1'b1),
.INJECTDBITERR ( injectdbiterr[bb] ),
.INJECTSBITERR ( injectsbiterr[bb] ),
.RDADDRECC ( rdaddrecc[bb] ),
.SBITERR ( sbiterr[bb] ),
//Port A Control Signals
.ADDRARDADDR ( raddr ), // 16-bit input: A port address/Read address
.ADDRENA (1'b1),
.CLKARDCLK ( clk_50 ), // 1-bit input: A port clock/Read clock
.ENARDEN ( rd_en ), // 1-bit input: A port enable/Read enable
.REGCEAREGCE ( rd_en ), // 1-bit input: A port register enable/Register enable
.RSTRAMARSTRAM ( 1'b0 ), // 1-bit input: A port set/reset
.RSTREGARSTREG ( 1'b0 ), // 1-bit input: A port register set/reset
.SLEEP (1'b0),
.WEA ( 4'h0 ), // 4-bit input: A port write enable
//Port A Data
.DINADIN ( wdata [64*(bb+1)-33:64*bb] ), // 32-bit input: A port data/LSB data
.DINPADINP ( ), // 4-bit input: A port parity/LSB parity
.DOUTADOUT ( rdata [64*(bb+1)-33:64*bb] ), // 32-bit output: A port data/LSB data
.DOUTPADOUTP ( ), // 4-bit output: A port parity/LSB parity
//Port B Control Signals
.ADDRBWRADDR ( waddr ), // 16-bit input: A port address/Read address
.ADDRENB (1'b1),
.CLKBWRCLK ( clk_50 ), // 1-bit input: B port clock/Write clock
.ENBWREN ( enbwren ), // 1-bit input: B port enable/Write enable
.REGCEB ( 1'b0 ), // 1-bit input: B port register enable
.RSTRAMB ( 1'b0 ), // 1-bit input: B port set/reset
.RSTREGB ( 1'b0 ), // 1-bit input: B port register set/reset
.WEBWE ( 8'hff ), // 8-bit input: B port write enable/Write enable
//Port B Data
.DINBDIN ( wdata [64*(bb+1)-1:64*bb+32] ), // 32-bit input: B port data/MSB data
.DINPBDINP ( ), // 4-bit input: B port parity/MSB parity
.DOUTBDOUT ( rdata [64*(bb+1)-1:64*bb+32] ), // 32-bit output: B port data/MSB data
.DOUTPBDOUTP ( ) // 4-bit output: B port parity/MSB parity
);

end
endgenerate


reg rd_en_vio;
reg enbwren_vio;
reg [15:0] injectdbiterr_vio;
reg [15:0] injectsbiterr_vio;
reg [1023:0] wdata_vio;
reg [14:0] raddr_vio;
reg [14:0] waddr_vio;

 

always@(posedge clk_50 or negedge reset)begin
if(!reset)begin
rd_en <= 0;
enbwren <= 0;
injectdbiterr <= 0;
injectsbiterr <= 0;
wdata <= 0;
raddr <= 0;
waddr <= 0;
end
else begin
rd_en <= rd_en_vio ;
enbwren <= enbwren_vio ;
injectdbiterr <= injectdbiterr_vio ;
injectsbiterr <= injectsbiterr_vio ;
wdata <= wdata_vio ;
raddr <= raddr_vio ;
waddr <= waddr_vio ;
end
end


vio_0 u_vio(
.clk (clk),
.probe_out0 (reset),
.probe_out1 (rd_en_vio),
.probe_out2 (enbwren_vio),
.probe_out3 (raddr_vio),
.probe_out4 (waddr_vio),
.probe_out5 (injectsbiterr_vio),
.probe_out6 (injectdbiterr_vio),

.probe_out7 (wdata_vio[127:0]),
.probe_out8 (wdata_vio[255:128]),
.probe_out9 (wdata_vio[383:256]),
.probe_out10 (wdata_vio[511:384]),
.probe_out11 (wdata_vio[639:512]),
.probe_out12 (wdata_vio[767:640]),
.probe_out13 (wdata_vio[895:768]),
.probe_out14 (wdata_vio[1023:896]),


.probe_in0 (rdata[127:0]),
.probe_in1 (rdata[255:128]),
.probe_in2 (rdata[383:256]),
.probe_in3 (rdata[511:384]),
.probe_in4 (rdata[639:512]),
.probe_in5 (rdata[767:640]),
.probe_in6 (rdata[895:768]),
.probe_in7 (rdata[1023:896])

);

endmodule

 

Here is my all signals.I capture BRAM signals in my VIO.

ila.pngvio.png

 

 

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Adventurer
Adventurer
264 Views
Registered: ‎05-30-2017

Okay, thanks. I cannot reproduce this problem on my end. Have you tried simulating? A couple of other suggestions...
1.) .WRITE_MODE_A ("Read_First"), should say .WRITE_MODE_A ("READ_FIRST"),
2.) Change your vio output declarations to be wires (not registers).
Lastly, I assume that you have asserted enbwren_vio at some point? This is necessary for the data to be written in.
Good luck...
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Visitor
Visitor
217 Views
Registered: ‎08-27-2018

Thanks,in my opinion,there are other resources not only bram was damaged.

I divided all the BRAM of my boards for three tests and found that the errors were concentrated in only a part of the area.It may be caused by someone connecting the 5V voltage to the IO before, depending on the resource distribution, the IO is located in this area.So there are other resources not only bram was damaged in this area.

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Moderator
Moderator
150 Views
Registered: ‎08-01-2007

Block Ram is senstive to voltage, timing, etc.

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