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Registered: ‎02-12-2019

sRIO example design does not establish linkup

I recently migrated a working sRIO design from a 7 series part (Vivado 2017.2) to an ultrascale (Vivado 2020.1) and I'm having a heck of a time getting the simulation to get a link established between two ports. The problem seems two fold: If the old design is moved into a newer version of Vivado, it no longer establishes a link in simulation. I can't even get the example design for any Ultrascale part to establish a link in simulation.

The simulation will run without really doing anything until about 8ms where it timesout.

It seems like I'm missing something. The documentation doesn't look like it has been updated since 2017 so it doesn't offer any hints about what might have been changed. A quick message board search shows that folks are using the core. Is anyone else running into this problem? 

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Xilinx Employee
Xilinx Employee
Registered: ‎05-01-2013

Could you just create a new SRIO Gen2 IP core example design in 2020.1 and run its simultion? Does it work?

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