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Contributor
Contributor
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Registered: ‎03-06-2016

some lanes show notintable error on my jesd204b board

Hi:
I am struggling dealing with notintable errors for my custom ad+fpga board.
the board has a v7-690t fpga and an AD9213 chip. the ad9213 has 16 lanes connecting to the fpga.
Each time I programme the fpga bit and configure the ad9213, There are always some lanes showing notintable error and disparity error.
for example: the first time, the lane 0,lane3,lane8 show no notintable errors,all the other lanes have notintable errors.
the second time, the lane 1,4,5,6,7,12 show no notintable errors,all the other lanes have notintable errors.
the third time, the lane 10,12,16 show no notintable errors,all the other lanes have notintable errors.
after I have programmed the fpga bit and configured the ad9213 for many times ,I doubt that all 16 lanes may not have signal integrity
issues.
We have checked the clock's signal quality ,also the power supply.
We do not have a higher sample rate oscilloscope,I noticed that the ad9213 can send prbs data ,so I've generated an ibert design to check eye scan
However, with no luck,all the lanes show no link. I wonder that the prbs generating differences between the ibert ipcore and the ad9213.
Any suggestions are appreciated.

 

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Moderator
Moderator
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Registered: ‎01-10-2019

Hi @gauss_work ,

Have you tried running the IBERT design in Near end loop back mode and check the EYE ?

Thanks,
Rahul Khatri
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