05-29-2020 01:31 PM
Hi, I am using Vivado 2019.2. I wanted to use a UARTLite in my in-development Microblaze on Spartan-7 design. Can I do that?
I tried to synthesize/simulate the IP AXI UART example design, which is pretty straightforward process. But when I simulated it, I got a flatline for TX and RX. And saw simulation error message:
[VRFC 10-3091] actual bit length 1 differs from formal bit length 4 for port 'wea' ["c:/wrk/2019.sub/2019.2.1/continuous/2019_12_05_2729669/packages/customer/vivado/data/ip/xilinx/axi_traffic_gen_v3_0/hdl/axi_traffic_gen_v3_0_rfs.v":13456]
So, did I miss a step? I guess I was hoping to see in the simulation, some sort of ascii char string being sent by the traffic generator out the TX port? Like "A" as mentioned in Implementing the Example Design, Chapter 5, p. 19?
Any clear tutorial/step by step would be appreciated. I am intending to bolt on the UARTLite to a Microblaze processor for implementation on a Spartan-7 #15 FPGA. Would this be possible?
05-29-2020 01:45 PM
Hi, if any one has a bit of additional time, could you look at the attached basic microblaze block diagram please? I simply generated what I thought would be useful blocks (basic MCU, basic I/O, basic UART) and want to know if I am heading in the right direction to make an equivalent of a basic MCU with TX, RX and Logic I/O design..