what is the first data of BRAM simulation result

[pligroup]

Hi all,

I use vivado 2015.4 to simulate the BRAM and I meet a problem. Please see the picture below,

the first data should be ffff0000 and the first data in the picture 000000 should be replaced XXXXXXX.

Why does it happen? the first data is 000000 and how to fix the problem? Thanks

li

[htsvn]

hi,

can you share the test-bench? Is this BRAM created out of an IP or is it a inferred BRAM?

--hs

[anusheel]

@pligroup

Are you using any very old primitive with Vivado? Also, are you using RTL to infer BRAM or using IP Catalog? 

Thanks,
Anusheel
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[pligroup]

Yes, I use coe file to initialize the BRAM. I attach the testbench and coe file. The BRAM is created from IP catalog. 

thanks

[pligroup]

@anusheel

I use vivado 2015.4. I use the IP catalog to infer the BRAM.

thanks

[pligroup]

@anusheel  @htsvn

I also find a strange thing. I add a signal called flag. When I start the BRAM, flag will become 1 at the first clock and then it will become 0. please see the picture below,

I use this to delete the 000000, but there is strange thing, when I zoom in the picture,

There still exists 00000 and the data is even changed not at the rising edge of clock.

Please give me some suggestion to fix the problem, 

thanks

[vemulad]

Hi @pligroup

Please attach block memory generator IP XCI file here.

[pligroup]

Hi @vemulad

Please see the attachment. Thanks.

[vemulad]

Hi @pligroup

There is no signal by name flag inside the IP. 

I tried creating a project with the files shared but I cannot run simulation due to this missing file BRAM_test. Can you share this file too?

[vemulad]

Hi @pligroup

Regarding the read to address zero, I was able to reproduce this issue in 2015.4. However when I migrated the project to 2016.2 I did not face this problem. Below is simulation result from vivado 2016.2. Can you try upgrading to 2016.2?

[pligroup]

Hi, @vemulad

I have third questions. 

first, I am a student, so can I directly upgrade the vivado to 2016.2 without license?

second, I attached my testbench and BRAM file, can you help me run this code at vivado 2016.2?

third, if the simulation result is not the same at vivado 2015.4 and Vivado 2016.2, will it be difference if I implement the code?

Thanks,

pengli

[vemulad]

Hi @pligroup

This is 2015.4 XSIM simulator issue.

You can use Questasim or modelsim with Vivado 2015.4 to get correct results.

[pligroup]

Hi @vemulad

Thank you for your help. So if I get the correct result at modelsim, then I download the bit stream into ZYNQ board with Vivado 2015.4, can I get the correct result? Besides, look at your picture, the first data is also ffff0000.

thanks

[vemulad]

Hi @pligroup

Yes, this should work fine in hardware.

[vemulad]

Hi @pligroup

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