xpm_fifo_sync read/write counts

[maxdz8]

Hello, I am experimenting with xpm_fifo_sync. I have observed something odd in my simulations and I am at a point in which I need the thing to work so I cannot delay getting this right.

According to ug953 v2018.2 (June 6, 2018):

wr_data_count[(WR_DATA_COUNT_WIDTH - 1) : 0]

rd_data_count[(RD_DATA_COUNT_WIDTH - 1) : 0]

and, on page 68

width is reported as RD_DATA_COUNT_WIDTH

and, on page 69

width is reported as WR_DATA_COUNT_WIDTH.

Everything good. But... if I instance my fifo this way:

wire[63:0] saved_twelve;
wire[3:0] saved_count;
wire save_wrok;
wire save_valid;
wire save_empty;
wire save_under;

wire save_rden = ...;
wire save_wren = ...;
wire[63:0] save_data_in;
wire[63:0] save_data_out;

xpm_fifo_sync # (
  .FIFO_MEMORY_TYPE          ("block"),
  .FIFO_WRITE_DEPTH          (16),
  .WRITE_DATA_WIDTH          (64),
  .WR_DATA_COUNT_WIDTH       (4),
  .PROG_FULL_THRESH          (12),
  .USE_ADV_FEATURES          ("1F1F"), //  wr_data_count, wr_ack, rd_data_count
  .FIFO_READ_LATENCY         (1),
  .READ_DATA_WIDTH           (64),
  .RD_DATA_COUNT_WIDTH       (4),
  .PROG_EMPTY_THRESH         (4)/*,
  .COMMON_CLOCK(1)*/
) load_saver (
  .sleep            (1'b0),
  .rst              (rst),
  .wr_clk           (clk),
  .wr_en            (save_wren),
  .din              (save_data_in),
  .rd_en            (save_rden),
  .dout             (save_data_out),
  .wr_data_count    (saved_count),
  .wr_ack(save_wrok),
  .data_valid(save_valid),
  .empty(save_empty),
  .underflow(save_under),
  .injectsbiterr    (1'b0),
  .injectdbiterr    (1'b0)
)

My simulation will look like:

If I declare wire[4:0] saved_count I'll get a spurious extra Z high bit but if I also declare WR_DATA_COUNT_WIDTH(5) and RD_DATA_COUNT_WIDTH(5) I get the right values.

I got this feel from the timing diagrams where it tries to pour out 16 as write or read data count. Those diagrams do not cite count width and reading again and again the documentation I missed the part where it gave requirements on values. Albeit it seemed reasonable the thing took the high bits of the true port, I think description is a bit lacking:

WR_DATA_COUNT_WIDTH - DECIMAL - 1 to 23  - 1  - Specifies the width of wr_data_count

As compared to

RD_DATA_COUNT_WIDTH - DECIMAL - 1 to 23 - 1 - Specifies the width of rd_data_count FIFO_READ_DEPTH = FIFO_WRITE_DEPTH * WRITE_DATA_WIDTH / READ_DATA_WIDTH

Which doesn't seem to be exactly the same thing either.

I wonder if this is truly expected or if I just missed it.

[pthakare · Accepted solution]

Hi @maxdz8

The formula in the user guide gives the FIFO read depth (i.e Maximum number of words can be read from the FIFO). 

The RD_DATA_COUNT_WIDTH formula should be

RD_DATA_COUNT_WIDTH  >   Log2(FIFO_READ_DEPTH) 

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[maxdz8]

I guess so. Document here reads the same. It seemed reasonable to me the macro would somehow cut the bits to my liking (rationale: I manage my data in blocks of 10dec elements so as long as I can count to 10dec all is good to me).