05-08-2019 09:12 AM - edited 05-08-2019 09:15 AM
I'm trying to implement Generative-Adversarial Neural Network(GAN) on my ZC706(Zynq xc7z045) Board using SDSoC, and I got some problems about lack of HW resources.
My GAN model is composed with 19 convolution layers, several pooling, concatenate layers, etc... and I want to HLS convolution layers with #HLS PRAGMAs, such as loop pipelining, unrolling, etc.
But, It seems xc7045 doesn't have enough HW resources(BRAM, LUT, etc...) to implement my GAN model.
I could HLS only 3 convolution layers from 19 convolution layers. HLS on more conv layers occured lack of resource errors.
So, what can I do to implement GAN on Zynq?
I'm thinking about these for solutions...
1. Buy Zynq Ultrascale+ Board (zcu102, zcu104...) which has more BRAMs, LUT, FF...
2. Use Xilinx supported fixed_point data type(such as ap_fixed, ap_int, etc...) and reduce HW resources.
3. Any other idea?
Need your supports!
Thank you and Good night.
06-02-2019 02:31 AM
It seems your design wont fit on ZC706. If you are interested on low cost MPSoC device [having more resources than Zynq 7000] then Ultra96 might be the option, else ZCU102/104 are awesome!
07-19-2019 07:58 AM
@jinsungroyYour approach is interesting and this is definitely an exciting development. I wanted to ask, have you also considered the approach of leveraging the Xilinx DPU IP and DNNDK flow for this development?
This flow natively supports INT8 quantization and scales from small to large Zynq and ZU+ devices. You would have to evaluate whether all of the layer parameters that you are require are supported, but certainly CONV, POOL, CONCAT are available.