Need to place bufg (automatically inserted in design by XST tool) outside hard macro
Board use: Virtex-6 FPGA ML605 Xilinx suite
Software: Xilinx ISE Project Navigator
Overview: The design is ring oscillator (will be use as sensor in my main project) which has one clock pin (clk) (others pins of no interest at the moment). The clock is used for multiple slice registers (flip flops). XST (xilinx synthesis tool) automatically inserts BUFG in design for clock net.
Task: My task right now is to create a hard macro for this design. So I can reuse it multiple times at different LOC's over board for placing sensors in my main project.
What I did: I am trying to create a hard macro by manually placing the registers and luts in CLBs.
1st bench of tries: manually placing of FF's and LUT's in CLBs. (but not placing BUFG) and then creating hard macro accordingly. (In hard macro deletion of the BUFG which later causes clock pins problem in the main project.
2nd bench of tries: Using option of "xilinx specific options" and forcing bufg to zero (0) in process properties of the xilinx synthesis tool and then manually placing registers and LUTs in CLBs using PlanAhead tool. After manual placement, when I rerun the implementation of the ring oscillator it takes more than 1 hour. It is taking too long time and I have tried creating hard macro and using it in my main project but it is not working properly.
Problem: How to cope bufg in hard macros? or How can I use move BUFG from inside my hard macro and use it outside in my main project for clock input.
I want to keep my hard macro BUFG free so I can reuse my ring oscillator sensor hard macro multiple times. Moreover, number of BUFG are limited.
Attached are the .vhd files and constraint file for manul placement of logic blocks as txt file (.ucf file is not allowed to upload so i saved it as .txt).