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Registered: ‎08-25-2019

Timing closure issue with the latest Xilinx DPU TRD when try to deploy it on ZCU102.

Hi there.

I downloaded the latest Xilinx DPU reference design

and ran the tcl script source ./trd_prj.tcl (in the folder pl/scripts) except I change the trd_prj.tcl line 75 into:

dict set dict_prj dict_param DPU_NUM {3},cause i want to deploy three DPU cores in my own project.

Then start Vivado 2019.1 and initial synthesis and implementaion processes.using strategy "Flow_PerfOptimized_high" and "Performance_ExplorePostRoutePhysOpt" for each process.the outcome was timing failure with approximate 2k endpoints not meet the timing requirement.

Wonder did anyone succeed run over the whole process using this TRD specified three DPU cores without any timing problem.and where did the FPGA.bin file come from packed in the image file petalinux-user-image-zcu102-zynqmp-sd-20190802.img.gz which deployed three DPU cores?

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