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Can ZYNQ's serdes receive this special signal?

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Observer
Posts: 42
Registered: ‎01-25-2014

Can ZYNQ's serdes receive this special signal?

The waveform will be the next.

__________...____________________________|`|________________________..._________________________|`|________________...

The pulse width is 400ps,that is to say 2.5Gbps. But the majority of time is zero.

Can ZYNQ's serdes receive this special signal?

Because ug476 reads "The 7 series FPGAs GTX and GTH transceivers are power-efficient transceivers, supporting line rates from 500 Mb/s to 12.5 Gb/s for GTX transceivers and 13.1 Gb/s for GTH transceivers.".

Can you help me?

Thanks in advance.

Moderator
Posts: 104
Registered: ‎05-02-2017

Re: Can ZYNQ's serdes receive this special signal?

hi @nanjing2002,

 

The pulse width looks okay but it has to be DC balanced. The electrical requirement mentioned in our datasheet should be met. Can you tell me if you are using some encoding/decoding on this signal? There is a run length requirement to be lesser than 512UI time.

 

 

Ta

Chandra

Observer
Posts: 42
Registered: ‎01-25-2014

Re: Can ZYNQ's serdes receive this special signal?

no encoding/decoding on this signal.The line rate is 2.5Gbps.So after parallel to serial by serdes,I expect 20bits@125MHz in the fabric logic.
Observer
Posts: 42
Registered: ‎01-25-2014

Re: Can ZYNQ's serdes receive this special signal?

@csattar

512UI and DC balanced?

Can you give me more detail information? Thanks.

Moderator
Posts: 104
Registered: ‎05-02-2017

Re: Can ZYNQ's serdes receive this special signal?

hi @nanjing2002,

 

512 UI is  the run length and Run length is how long a serial transceiver link sends an unbroken string of 0's or 1's. The attribute is listed in the datasheet as Run length (CID) for how long it takes the CDR to lose lock to the clock when using lock to data.

 

regarding the DC balance

 

8b10b and 64b66b do a whole bunch of things - not just DC balance.

 

In fact, the most important thing that these do is ensure transition density. The transceiver uses Clock/Data recovery (CDR). In order for this to work there must be a minimum transition density, or a maximum Continuous Identical Digit (CID). The CDR uses each transition in the datastream to recover the phase of the implied clock. Between transitions, the CDR runs open loop, and can drift over a number of bits. At some point the CDR will have drifted away from the "correct" bit rate, and the sampling position of the data will move out of the center of the data eye. Once transitions start again, the CDR will recover, but during that time, bits may be mis-sampled, or if the drift is large enough, bits can even be replicated or dropped.

 

So, you need some mechanism to ensure maximum CID. In 8b10b, the maximum is (I believe) 5 bits. In 64b66b it is 65, but due to scrambling it is statistically lower than that.

 

DC balance is a second issue, but is only a problem if the serial link is AC coupled. With AC coupling, a 0/1 disparity will eventually charge up or discharge the coupling capacitor, causing the differential voltages of the P/N pair to move away from eachother - again causing mis-sampling.

 

You don't have to use 8b10b or 64b66b (or 64b67b) or any other "standard" mechanism of coding - as long as your coding can

  - recover framing of the serial stream

  - guarantee a maximum CID

  - provide DC balance (if the link is AC coupled)

  - provide mechanisms for channel bonding (if multiple channels are used)

  - provide mechanisms for rate matching (if you are not running your receiver on the recovered clock)

  - (and maybe one or two I have forgotton)

 

But - 8b/10b is really easy - the GT takes care of the whole thing for you - all you have to do is run the link at 25% faster than your data rate. Unless, of course,  you are already near the maximum data rate for the GT.

 

thanks

Chandra sekhar

Observer
Posts: 42
Registered: ‎01-25-2014

Re: Can ZYNQ's serdes receive this special signal?

@csattar

Thaks for your reply.

The serdes design dont use CDR.

Even it dont use PCS(8b10b/64b66b)

Moderator
Posts: 104
Registered: ‎05-02-2017

Re: Can ZYNQ's serdes receive this special signal?

hi @nanjing2002,

 

can you let me know how your achieving the DC balance with out using the encoding ?

 

 

thanks

S.chandra sekhar

Observer
Posts: 42
Registered: ‎01-25-2014

Re: Can ZYNQ's serdes receive this special signal?

@csattar

The PCB design was not created by us. It comes from one of my customers. I'm confused with it too.

The usage of serdes on the PCB design is very special. However, the customer is very confident that the design is no problem. He do want only receive signal.

 

Moderator
Posts: 104
Registered: ‎05-02-2017

Re: Can ZYNQ's serdes receive this special signal?

hi @nanjing2002

 

can you let me know any error message is seen or any issue . now coming down to receiver signal query can you throw some light how he is transmitting the TX  signal with parameters and specification used .

 

 

ta

sekhar

Moderator
Posts: 104
Registered: ‎05-02-2017

Re: Can ZYNQ's serdes receive this special signal?

hi @nanjing2002.,

 

Many protocols use 8B/10B encoding on outgoing data. 8B/10B is an industry standard encoding scheme that trades two bits overhead per byte for achieved DC-balance and bounded disparity to allow reasonable clock recovery. The GT transceiver has a built-in 8B/10B TX path to encode TX data without consuming device resources. Enabling the 8B/10B encoder increases latency through the TX path. The 8B/10B encoder can be disabled or bypassed to minimize latency, if not needed.

 

8B/10B encoding includes a set of Data characters and K characters. Eight-bit values are coded into 10-bit values, keeping the serial line DC balanced. K characters are special Data characters designated with a CHARISK. K characters are used for specific informative.

 

so it always recommended to use encoding scheme.

 

 

thanks

s.chandra sekhar

 

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