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How to use the clock gererated from PS in the PL?

Accepted Solution Solved
Observer
Posts: 34
Registered: ‎09-16-2013
Accepted Solution

How to use the clock gererated from PS in the PL?

Hi all,

I've already configured PS to make it output FCLK_CLK0 to PL, and instantiated the PS module in the top level RTL file.As the FCLK_CLK0 signal is an output from PS , then I defined it as a wire at top level, and used FCLK_CLK0 as PL's system clock, but during the process of generating bitsream, there is an error:

[Drc 23-20] Rule violation (RTSTAT-1) Unrouted net - 1net(s) are unrouted. The problem net(s) are system_wrapper_inst/system_i/processing_system7_0/inst/PS_CLK.

 

How to use the clock from PS in PL? Why the  FCLK_CLK0 signal can not be routed?

Do I need to add some constraints?  Thanks a lot.

 


Accepted Solutions
Scholar
Posts: 1,180
Registered: ‎11-09-2013

Re: How to use the clock gererated from PS in the PL?

It just works.

 

modifying the top level is not recommended technology when you use vivado, in order to take full advantages you should wrap all you IP into Vivado IP and let IPI to manage the connectivity between IPs

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All Replies
Scholar
Posts: 1,180
Registered: ‎11-09-2013

Re: How to use the clock gererated from PS in the PL?

It just works.

 

modifying the top level is not recommended technology when you use vivado, in order to take full advantages you should wrap all you IP into Vivado IP and let IPI to manage the connectivity between IPs

Observer
Posts: 34
Registered: ‎09-16-2013

Re: How to use the clock gererated from PS in the PL?

Yes, it works , I forgot to make the FCLK_CLK0 as a output port in the block design. thank you very much!