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Read/Write memory with AXI master

Observer
Posts: 21
Registered: ‎07-17-2017

Read/Write memory with AXI master

Hi All,

i'm an italian student working on the ZedBoard Zynq-7000. 

My goal, for now, is to create a custom IP that reads some data from DDR/BRAM and writes this data to another location in the BRAM.

Since now, i've created a simple IP using vivado HLS, that creates two AXI master interfaces, one for the reads and one for the writes. Afterwards i've created a design in Vivado design suite, that i've attacched in the post. after that i've created a simple bare metal application for trying this design. This application creates a 320x240 matrix (the dimension of data that i need to transfer) in the DDR and try to copy this data to BRAM, but the data  are not transfered. 

I've searched for online solutions but i have not found anything that could help me, so i ask for help here, since my work is stopped right now. 

 

I attach the vivado HLS code for the IP, the vivado design and the c application to run on the board.

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Xilinx Employee
Posts: 2,016
Registered: ‎11-09-2015

Re: Read/Write memory with AXI master

Hi @anto95,

 

This is not using HLS and this is not accessing the DDR memory (but the OCM) but you can have a look to this wiki page I have written last month:

http://www.wiki.xilinx.com/Zynq-7000+AP+SoC+-+Read+and+Write+to+the+Zynq+OCM+from+The+PL

 

The IP is doing write/read-back into the OCM memory of the zynq. You can change a bit the code of the IP to read and then write data. And then just change the address to point to the DDR.

 

Hope that helps,

 

Regards,

 

Florent

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Observer
Posts: 21
Registered: ‎07-17-2017

Re: Read/Write memory with AXI master

Thanks @florentw for the reply, 

 

I went through all of your tutorial and it worked, but i don't know how to modify the source code of the IP for make it read data before writing it. I need to use vivado HLS since i don't know any language such verilog or vhdl. I need to be able to reprogram the addresses from where to read and write the data, and from what i've seen the IP you mentioned has a fixed addres from where to store the data. 

 

In addition to this, i've tried to continue with my IP mentioned in my first post, and i've managed to get some data transfered, but the problem now is that some data are not transfered. For example: i create in the OCM an array of length 1000 containing '1' (a char) and i use my IP to copy these 1000 elements to some other location in the OCM. The data are transfered but not all of them. I check this by doing a crc (sum of the data copied). This can also be checked by viewing the memory in the debugger. I have some "holes" in which data are not being copied. Maybe is this a problem with synchronization beetween reads and writes?? 

 

I attach the code (copia_mem.c) of my custom IP and the code (main.c) used to test the IP.

 

Thanks for the help, Antonio

Xilinx Employee
Posts: 2,016
Registered: ‎11-09-2015

Re: Read/Write memory with AXI master

Hi @anto95,

 

2 things to investigate:

-> cache coherency

-> 4K AXI limit boundary. Make sure you are not writing over 4K boundary. For example, you cannot do a single write from 0x4000FFF0 to 0x400100C.

 

Regards,

 

Florent

 

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