UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Reply

Using on PL, a Clock generated by PS on MicroZed Board with Zynq 7020

Accepted Solution Solved
Newbie
Posts: 2
Registered: ‎03-05-2014
Accepted Solution

Using on PL, a Clock generated by PS on MicroZed Board with Zynq 7020

I am using the MicroZed board I pretend to develop some logic, to implement on PL side of Zynq 020, and I just want to use the PS to generate the clock to PL within the FPGA.

With the ISE, I instantiated the Processor System and opened it.

With XPS, I defined a clock of 50MHz on FCLK_CLK0, with IO PLL source, and defined it as an external port.

I closed the XPS and on ISE I generated the Top Level of the Processing System.

In the FPGA top level, I connected all “Processing System Top Level” ports to FPGA ports and the clk output to my logic (within PL) and also connected the FCLK_CLK0 to a FPGA output.

I generated the bitstream and downloaded the .bit file into the FPGA with success.

After these steps I verified that I do not have a clocking signal at FPGA output. The signal is stuck at High.

Are there some missing steps in my design flow?


Accepted Solutions
Xilinx Employee
Posts: 26
Registered: ‎02-26-2014

Re: Using on PL, a Clock generated by PS on MicroZed Board with Zynq 7020

Hi pbento,

 

Are you running FSBL before checking the clock?

 

If not, you have to export the hardware from XPS, and generate the FSBL in SDK.

See http://www.wiki.xilinx.com/Build+FSBL to generate FSBL.

View solution in original post


All Replies
Xilinx Employee
Posts: 26
Registered: ‎02-26-2014

Re: Using on PL, a Clock generated by PS on MicroZed Board with Zynq 7020

Hi pbento,

 

Are you running FSBL before checking the clock?

 

If not, you have to export the hardware from XPS, and generate the FSBL in SDK.

See http://www.wiki.xilinx.com/Build+FSBL to generate FSBL.