Re: pipeline concept in Xilinx
05-19-2017 07:24 PM
@liuz3 pipelining is most useful when input is available in a streaming fashion and the output is not necessary to make decision on what to do next. In your example it would make sense to have one stage of pipeline to have the multipliers run and another stage for the adder. ie
pmul1 <= p1*p2;
pmul2 <= p3*p4;
psum <= pmul1 + pmul2;
The benefit of this schedule is that in the original design, the period of the logic is Tmul + Tadd but in the second one max(Tmul, Tadd) (which is most likely Tmul). So we managed to reduce the period of the design at the expense of some latency. If p1, p2, p3 & p4 are available every cycle, we will get the first output 2 cycles later and then one sum every cycle after that so the overall through will increase (because of the reduced period, ie increased frequency.)
PS of course in a "real" design, one would split up the multiplier into stages so that all pipeline stages would be of equal depth and each stage would fit into the desired period perfectly.
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