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Any examples of JESD PHY DRP configuration? - ( ‎01-22-2021 05:00 AM )

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Virtex-6 GTX IP Sim. error - ( ‎11-22-2020 09:40 PM )

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7-series GTX IBERT Example Design @ 0.625 Gbps - ( ‎11-16-2020 04:50 PM )

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Kintex-7 10G-Ether PHY: About sharing coreclk and ... - ( ‎11-01-2020 11:08 PM )

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Nonlinearity of eye scan function (Kintex-7 GTX t... - ( ‎07-14-2020 01:07 AM )

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Dip in eye scan using DFE (Kintex-7 GTX transceive... - ( ‎06-26-2020 01:05 AM )

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ALIGN primitive in 7series GTX as sata - ( ‎03-18-2020 06:25 AM )

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Multi-lane GTX Transmitter Alignment - ( ‎02-27-2020 12:30 PM )

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Error in SD-SDI transmission using GTX - ( ‎02-18-2020 06:22 AM )

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Instantiating the IBERT 7 series GTX IP core - ( ‎02-07-2020 09:50 AM )

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7 Series GTX - ( ‎11-11-2019 02:11 PM )

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GTX CPLL occasionally not locking on powerup - ( ‎10-18-2019 10:39 AM )

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MUXing 4:1 GTX clock unroutable placement - ( ‎09-04-2019 11:47 PM )

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Scrambled data on GTX - ( ‎08-07-2019 02:14 AM )

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About COMMA detect in Virtex6 GTX - ( ‎05-14-2019 09:28 PM )

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GTX transceiver in Kintex Ultrascale - ( ‎04-30-2019 03:02 PM )

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ZC706 GT Serial TxRx - ( ‎04-25-2019 10:31 AM )

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GTX, GTY far-end PCS - ( ‎03-27-2019 01:15 AM )

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Aurora 64b66b MMCM and GTX locking - ( ‎12-04-2018 02:13 AM )

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7 Series GTX minimum line rate workaround - ( ‎10-17-2018 10:56 AM )

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Re: Preventing Vivado Synthesis removing un-driven... - ( ‎10-08-2018 02:49 AM )

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How to configure a GTX to support 10.0, 5.0, 2.5 ... - ( ‎08-23-2018 09:11 AM )

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RapidIO at 3.125Gbps can't link smoothly between X... - ( ‎07-16-2018 12:04 AM )

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Configuring 7 series FPGA Transceiver wizard for V... - ( ‎06-13-2018 06:35 AM )

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Re: Virtex7 GTX transcievers wouldn't lock - ( ‎05-04-2018 10:10 AM )

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[7 Series GTX] RXUSRCLK2, RXUSRCLK, and RXOUTCLK t... - ( ‎03-13-2018 05:49 AM )

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GTX TX buffer bypass and multiple channels - ( ‎02-13-2018 11:46 AM )

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Eyescan CSV Header has invalid format [Labtools 27... - ( ‎02-05-2018 07:37 AM )

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Two CPRI cores in the same GTX? xc7z030ffg676-2 - ( ‎01-09-2018 01:59 AM )

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What does 'biased' mean for MGTXRXP/N pin on Table... - ( ‎11-27-2017 10:43 PM )

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Info: jitter integration bandwidth when using GTX/... - ( ‎09-22-2017 02:40 AM )

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GTX Transceiver CPLLFBCLKLOST - ( ‎07-27-2017 03:25 AM )

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jesd 204 channel bonding - ( ‎06-12-2017 06:09 AM )

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Setting GTX Attributes with IBERT - ( ‎06-09-2017 08:26 AM )

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7 series GTX : Disable Rx EQ - ( ‎05-31-2017 02:11 AM )

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GTX IO standards - ( ‎04-06-2017 06:49 AM )

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Aurora 8b10b only receiving sequence 0x4a4a - ( ‎03-02-2017 03:30 AM )

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GTX Transceiver design not working with latest too... - ( ‎12-16-2016 01:33 PM )

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Virtex-7 GTX: Feeding REFCLK from another RX chann... - ( ‎11-02-2016 09:21 AM )

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How do I enable the PCS functionality of GTX - 7 s... - ( ‎09-19-2016 10:53 PM )

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7Series Transceiver GTX Pattern checker - ( ‎09-05-2016 04:36 AM )

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IBERT 7 series issue - ( ‎08-24-2016 12:34 AM )

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CDR of 7 Series GTX - ( ‎08-15-2016 09:12 PM )

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7 Series GTX QPLL doubts - ( ‎08-10-2016 03:23 AM )

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Tuning of GTX Receiver for Custom Protocol - ( ‎08-04-2016 01:10 AM )

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Question About Unused GTX Pins - ( ‎07-14-2016 12:26 PM )

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When to schedule DRP operation - ( ‎07-14-2016 03:40 AM )

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RATE change in GTX zynq-706 - ( ‎07-12-2016 09:56 PM )

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GTX clock robustness lost after 2013.3 to 2015.4 V... - ( ‎05-25-2016 08:37 PM )

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DisplayPort sink with SSC on a kintex-7 FPGA. - ( ‎02-09-2016 09:04 AM )

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